DS565 Datasheet, PDF (3/28 Pages) Xilinx, Inc – PLBV46 Master Burst

PLBV46 Master Burst (v1.01a)
it may assert the dst_dsc_n to discontinue the transfer. Conversely, the Source may terminate transmission
prematurely with the assertion of the src_dsc_n signal.
Note: The current implementation of the PLBV46 Master Burst does not support discontinue assertion by the Client IP
LocalLink interface. See the I/O signal descriptions of the individual discontinue signals inTable 1.
The rem[0:n] signal (short for remainder) is set by the Source during each data beat in which a delimiter flag is set
(sof_n, sop_n, eop_n, eof_n). The value asserted specifies the valid bytes in that data beat and are somewhat
application specific depending on the needs of the source and destination devices. The rem can be either an
encoded value or a masked value and either active high or active low assertion levels. For the PLBV46 Master
Burst, the rem bits are always a mask representation and active low assertion levels. Byte lane ordering follows
PLB byte lane ordering.
A basic LocalLink data transfers are shown in Figure 2. The data packet consists of 16 data beats of 32 bits wide. The
diagram shows both the Source and Destination throttling the transfer. In this case, the sop_n and eop_n are not
shown because header and footer data is not being transmitted in the packet,
Note: Note: The Xilinx LocalLink Interface specification allows the use of either right-to-left or left-to-right bit ordering as long
the Source and Destination are consistent. The PLBV46 Master Burst follows the IBM CoreConnect convention of left-to-right bit
ordering and Big Endian byte ordering.
X-Ref Target - Figure 2
0ns
100ns
200ns
300ns
400ns
500ns
600ns
700ns
800ns
clk
sof_n
eof_n
src_rdy_n
dst_rdy_n
d[0:31]
dst_dsc_n
src_dsc_n
0 123
4
5 6 7 8 9 10 11 12 13 14 15
Figure 2: Basic LocalLink Transfer
DS565 December 14, 2010
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