DS565 Datasheet, PDF (5/28 Pages) Xilinx, Inc – PLBV46 Master Burst

PLBV46 Master Burst (v1.01a)
Table 1: PLBV46 Master Burst I/O Signal Description
Signal Name
Interface Signal Type Init Status
Description
M_lockerr
PLB Bus
O
0
Unused. See Note 2.
M_abort
PLB Bus
O
0
Unused. See Note 2.
M_UABus(0:31))
PLB Bus
O
zeros
Unused. See Note 2.
PLB_MBusy
PLB Bus
I
Unused. See Note 2.
PLB_MIRQ
PLB Bus
I
Unused. See Note 2.
PLB_RdWdAddr(0:3)
PLB Bus
I
Unused. See Note 2.
IPIC Command Interface Signals
IP2Bus_MstRd_Req
IPIC
I
User Logic Read Request.
IP2Bus_MstWr_Req
IPIC
I
User Logic Write Request.
IP2Bus_Mst_Addr(0 to
C_MPLB_AWIDTH-1)
IPIC
I
User Logic Request Address.
See Note 4.
IP2Bus_Mst_BE(0 to
IPIC
I
[C_MPLB_NATIVE_DWIDTH/8]-1)
User Logic Request Byte Enables
(only used during single data beat
requests).
IP2Bus_Mst_Length(0 to 11)
IPIC
I
User Logic Request Length (bytes)
for Fixed Length Burst Transfers.
See Note 4.
IP2Bus_Mst_Type
IPIC
I
User Logic Request Type Indicator
0 = Single Data Beat
1 = Fixed Length Burst
See Note 5.
IP2Bus_Mst_Lock
IPIC
I
Reserved: Tie to logic Low.
User Logic Bus Lock Request.
IP2Bus_Mst_Reset
IPIC
I
Optional User Logic Reset.
Request.
Bus2IP_Mst_CmdAck
IPIC
O
0
Command Acknowledge Status.
Bus2IP_Mst_Cmplt
IPIC
O
0
Command Complete Status.
Bus2IP_Mst_Error
IPIC
O
0
Command Error Status.
Bus2IP_Mst_Rearbitrate
IPIC
O
0
Command Rearbitrate Status.
User Logic should ignore this
signal.
Bus2IP_Mst_Timeout
IPIC
O
0
Command Timeout Status.
IPIC Read LocalLink Interface Signals
Bus2IP_MstRd_d(0 to
C_MPLB_NATIVE_DWIDTH-1)
IPIC
O
zeros
Read data output to User Logic.
Bus2IP_MstRd_REM(0 to
IPIC
O
zeros
LocalLink Remainder Indicators
[C_MPLB_NATIVE_DWIDTH/8]-1)
(Mask format, active low).
See Note 6.
Bus2IP_MstRd_sof_n
IPIC
O
1
Active low signal indicating the
starting data beat of a Read
LocalLink transfer.
DS565 December 14, 2010
www.xilinx.com
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Product Specification