DS565 Datasheet, PDF (7/28 Pages) Xilinx, Inc – PLBV46 Master Burst

PLBV46 Master Burst (v1.01a)
Table 1: PLBV46 Master Burst I/O Signal Description
Signal Name
Interface Signal Type
Bus2IP_MstWr_dst_rdy_n
IPIC
O
IP2Bus_MstWr_dst_dsc_n
IPIC
O
Init Status
Description
1
Active low signal indicating that the
data value asserted on the
IP2Bus_MstWr_d Bus is being
accepted by the LocalLink
destination (Master).
1
Active low signal indicating that the
Write LocalLink Destination
(Master) needs to discontinue the
transfer. This will only be asserted
if the Master encounters a PLB
Timeout during the address phase
of a parent or child request to the
PLB.
Note 1
This signal’s function and timing is defined in the IBM^® 128-Bit Processor Local Bus Architecture Specification
Version 4.6.
Note 2
Output ports that are not used are driven to constant logic levels that are consistent with the inactive state for the
subject signal. Input ports that are required but not used are internally ignored by the design.
Note 3
For fixed length burst requests, the starting address for the request as specified by the IP2Bus_Mst_Addr(0:31)
input must be aligned on an address boundary matching the C_MPLB_NATIVE_DWIDTH value.
Note 4
The request length is specified in bytes and must be a multiple of C_MPLB_NATIVE_DWIDTH/8.
Note 5
The requested data transfer width for a fixed length burst request will be automatically set to the native data width
of the Master which is assigned with the C_MPLB_NATIVE_DWIDTH parameter.
Note 6
The PLBV46 Master Burst only supports Mask representation (as opposed to encoded representation) for values on
the LocalLink REM buses. In addition, the REM values must be asserted active low.
DS565 December 14, 2010
www.xilinx.com
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Product Specification