DS565 Datasheet, PDF (22/28 Pages) Xilinx, Inc – PLBV46 Master Burst

PLBV46 Master Burst (v1.01a)
Burst Write With Burst Length Expansion
A Fixed Length Burst write of 4 Quad-words that requires Burst length Expansion is shown in Figure 14. The
Master’s Native Data Width is set to 128 and it attempts to burst write 4 quad words to a 32-bit Slave. This scenario
requires the Master (and the target Slave) to expand the required number of PLB data beats from 4 to 16 to complete
the requested data transfer. The Master will collect a quad word from the Write LocalLink and then output 4 data
beats (1 word per data beat) onto the PLB (that is all the 32-bit Slave will consume per data beat). This behavior
repeats until the transfer is completed.
X-Ref Target - Figure 14
0ns
MPLB_Clk
100ns 200ns 300ns 400ns 500ns
M_request
M_buslock
M_priority1[0:1]
M_MSize[0:1]
M_ABus[0:31]
M_BE[0:15]
M_RNW
M_size[0:3]
M_type[0:2]
M_wrDBus[0:127]
M_wrBurst
M_rdBurst
00
0
10000004
'h3000
'b1100
'b000
WD0
PLB_MaddrAck
PLB_MSsize[0:1]
00
PLB_MRearbitrate
PLB_MBusy
PLB_RdDBus[0:127]
PLB_MRdDAck
PLB_MWrDAck
PLB_MWrErr
PLB_MRdErr
PLB_RdBTerm
PLB_WrBTerm
IP2Bus_MstRd_Req
IP2Bus_MstWr_Req
IP2Bus_Mst_Type
IP2Bus_Mst_Addr[0:31]
IP2Bus_Mst_BE[0:15]
IP2Bus_Mst_Length[0:11]
IP2Bus_Mst_Lock
IP2Bus_Mst_Reset
10000004
'hXXXX
040
Bus2IP_Mst_CmdAck
Bus2IP_Mst_Cmplt
Bus2IP_Mst_Error
Bus2IP_Mst_Rearbitrate
Bus2IP_Mst_Cmd_Timeout
Bus2IP_MstRd_d[0:127]
Bus2IP_MstRd_REM[0:15]
Bus2IP_MstRd_sof_n
Bus2IP_MstRd_eof_n
Bus2IP_MstRd_src_rdy_n
Bus2IP_MstRd_src_dsc_n
IP2Bus_MstRd_dst_rdy_n
IP2Bus_MstRd_dst_dsc_n
IP2Bus_MstWr_d[0:127]
IP2Bus_MstWr_REM[0:15]
IP2Bus_MstWr_sof_n
IP2Bus_MstWr_eof_n
IP2Bus_MstWr_src_rdy_n
IP2Bus_MstWr_src_dsc_n
Bus2IP_MstWr_dst_rdy_n
Bus2IP_MstWr_dst_dsc_n
QWD0 QWD1 QWD2 QWD3
'h0000
Figure 14: Burst Write Resulting in Burst Length Expansion
DS565 December 14, 2010
www.xilinx.com
22
Product Specification