DS565 Datasheet, PDF (10/28 Pages) Xilinx, Inc – PLBV46 Master Burst

PLBV46 Master Burst (v1.01a)
Parameter Detailed Descriptions
C_MPLB_AWIDTH
This integer parameter is used by the PLBV46 Master Burst to size internal address related components and the
input address from the User logic on the Command Interface. The parameter is provided for future growth beyond
32-bit addressing. Currently, the parameter value is only allowed to be set 32.
C_MPLB_DWIDTH
This integer parameter is used by the PLBV46 Master Burst to size and optimize the PLBV46 data bus interface
logic. This value should be set to match the actual width of the PLBV46 bus, 32, 64 or 128-Bits.
C_MPLB_NATIVE_DWIDTH
This integer parameter is used to specify the internal data width of the PLBV46 Master Burst as well as the IPIC data
width to the User Logic. The parameter may be set to 32, 64, or 128.
C_MPLB_SMALLEST_SLAVE
This parameter is defined as an integer and is set to the smallest Native Data Width of any Slave that is attached to
the same PLBV46 bus as the Master. Allowed values are 32, 64, and 128. The parameter is used when the Master is
parameterized with a Native Data Width of 64 or 128 bits. If the value of the C_MPLB_SMALLEST_SLAVE is less
than the Native Data Width of the Master, then Conversion Cycle and Burst Length Expansion logic is
automatically included in the Master’s implementation.
C_INHIBIT_CC_BLE_INCLUSION
This parameter is used to inhibit the automatic inclusion of the Conversion Cycle and Burst Length Expansion logic
if it is known by the User that the Master will not be accessing the narrower Slaves or the requested transfer widths
for any access will not exceed the Native Data Width of any targeted Slave.
C_FAMILY
This parameter is defined as a string. It specifies the target FPGA technology for implementation of the PLB Slave.
This parameter is required for proper selection of FPGA primitives. Currently, the PLBV46 Master Burst does not
implement any FPGA primitives that require the use of this parameter.
IPIC Transaction Timing
The following section shows timing relationships for PLBV46 and IPIC interface signals during read and write
transfers. Single data beat and Fixed Length Burst transfers are shown.
DS565 December 14, 2010
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Product Specification