DS565 Datasheet, PDF (1/28 Pages) Xilinx, Inc – PLBV46 Master Burst

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PLBV46 Master Burst (v1.01a)
DS565 December 14, 2010
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Product Specification
Introduction
The PLBV46 Master Burst is a continuation of the Xilinx
family of IBM CoreConnect compatible LogiCORE
products. It provides a bi-directional interface between
a User IP core and the PLB v4.6 bus standard. This
version of the PLBV46 Master Burst has been designed
for PLBV46 Master operations consisting of single data
beat read or write transfers and Fixed Length Burst
Transfers of 2 to 16 data beats.
Features
• Compatible with IBM CoreConnect 32, 64 and
128-bit PLB
• Parameterizable data width of Client IP Interface
(IPIC) to 32, 64, or 128 bits
• Supports Single Beat Read and Write data transfers
up to the IPIC data width
• Automatic Conversion Cycle support for
single data beat transfers to/from narrower
PLB Slave devices
• Supports Fixed Length Burst Read and Write data
transfers of 2 to 16 data beats on the PLB
• Transfer width is equal to the parameterized
IPIC data width
• Automatic Burst Length Adjustment for
bursting to/from narrower PLB Slave devices
• The User interface consists of a Command/Status
interface and Read and Write LocalLink interfaces
for the data transfer
• LocalLink transfers can be 1 to 4092 bytes in
length with data width equal to the IPIC data
width
• The Master will automatically break IP Client
transfer requests requiring more than 16 data
beats into multiple fixed length bursts (2 to 16
data beats) on the PLB
LogiCORE IP Facts Table
Supported
Device Family
Core Specifics
Virtex^®-6, Virtex-5, Virtex-4, Spartan^®-6,
Spartan-3E, Automotive Spartan-3E, Spartan-3,
Automotive Spartan-3, Spartan-3A, Automotive
Spartan-3A, Spartan-3A DSP, Automotive
Spartan-3A DSP
Supported User
Interfaces
PLBV46, LocalLink
Supported
Operating
Systems
Windows XP Professional 32-Bit/64-Bit, Windows
Vista Business 32-Bit/64-Bit, Red Hat Enterprise
Linux WS v4.0 32-bit/64-bit, Red Hat Enterprise
Desktop v5.0 32-bit/64-bit (with Workstation
Option), SUSE Linux Enterprise (SLE) desktop and
server v10.1 32-bit/64-bit
Resources
Configuration
LUTs
FFs
DSP Block
Slices RAMs
Max.
Freq.
263-645 107-194 161-376 None
Provided with Core
Documentation
Product Specification
Design File
Formats
VHDL
Constraints File
None
Instantiation
Template
VHDL Wrapper
Reference
Designs &
Application
Notes
None
Design Tool Requirements
Xilinx
Implementation
Tools
ISE^® 12.4
Verification
Mentor Graphics ModelSim 6.5c
Simulation
Mentor Graphics ModelSim 6.5c
Synthesis Tools
XST
Support: Provided by Xilinx, Inc.
© Copyright 2009-2010 Xilinx, Inc. XILINX, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, and other designated brands included herein are trademarks of Xilinx
in the United States and other countries. All other trademarks are the property of their respective owners.
DS565 December 14, 2010
www.xilinx.com
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Product Specification