DS565 Datasheet, PDF (20/28 Pages) Xilinx, Inc – PLBV46 Master Burst

PLBV46 Master Burst (v1.01a)
Write Conversion Cycle
A single data beat write operation that requires Conversion Cycles is shown in Figure 12. The Master’s Native Data
Width is set to 128 and it attempts to write 13 bytes to a 32-bit Slave. This scenario requires the Master to initiate 3
Conversion Cycles to complete the needed data transfer.
X-Ref Target - Figure 12
0ns
MPLB_Clk
100ns
200ns
300ns
M_request
M_buslock
M_priority
M_MSize[0:1]
M_ABus[0:31]
M_BE[0:15]
M_RNW
M_size[0:3]
M_type[0:2]
M_wrDBus[0:127]
M_wrBurst
M_rdBurst
'b01
b'11
'b10
10000003 10000004 10000008 1000000C
1FFF 0FFF 00FF 000F
0
0
WRD0123
PLB_MaddrAck
PLB_MSsize[0:1]
PLB_MRearbitrate
PLB_MBusy
PLB_RdDBus[0:127]
PLB_MRdDAck
PLB_MWrDAck
PLB_MWrErr
PLB_MRdErr
PLB_RdBTerm
PLB_WrBTerm
00 00 00 00
IP2Bus_MstRd_Req
IP2Bus_MstWr_Req
IP2Bus_Mst_Type
IP2Bus_Mst_Addr[0:31]
IP2Bus_Mst_BE[0:15]
IP2Bus_Mst_Length[0:11]
IP2Bus_Mst_Lock
IP2Bus_Mst_Reset
10000003
0001111111111111
XXX
Bus2IP_Mst_CmdAck
Bus2IP_Mst_Cmplt
Bus2IP_Mst_Error
Bus2IP_Mst_Rearbitrate
Bus2IP_Mst_Cmd_Timeout
Bus2IP_MstRd_d[0:127]
Bus2IP_MstRd_REM[0:15]
Bus2IP_MstRd_sof_n
Bus2IP_MstRd_eof_n
Bus2IP_MstRd_src_rdy_n
Bus2IP_MstRd_src_dsc_n
IP2Bus_MstRd_dst_rdy_n
IP2Bus_MstRd_dst_dsc_n
IP2Bus_MstWr_d[0:127]
IP2Bus_MstWr_REM[0:15]
IP2Bus_MstWr_sof_n
IP2Bus_MstWr_eof_n
IP2Bus_MstWr_src_rdy_n
IP2Bus_MstWr_src_dsc_n
Bus2IP_MstWr_dst_rdy_n
Bus2IP_MstWr_dst_dsc_n
WRD0123
0000
400ns
Figure 12: Single Data Beat Write Resulting in Conversion Cycles
DS565 December 14, 2010
www.xilinx.com
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Product Specification