DS565 Datasheet, PDF (11/28 Pages) Xilinx, Inc – PLBV46 Master Burst

PLBV46 Master Burst (v1.01a)
Single Data Beat Read Operation
Two single beat read cycles are shown in Figure 3. The Master has a Native Data Width of 32 bits and the PLB data
width is 32 bits. The first cycle shows the PLB Slave address and data acknowledging the read cycle at the earliest
allowed times by the PLB specification. The second read transfer indicates a more typical address acknowledge
sequence and a delayed read data acknowledge by the PLB Slave device.
X-Ref Target - Figure 3
0ns
MPLB_Clk
100ns
200ns
300ns
400ns
M_request
M_buslock
M_priority
1
M_MSize[0:1]
0
M_ABus[0:31]
M_BE[0:3]
0011
M_RNW
M_size[0:3]
0
M_type[0:2]
0
M_wrDBus[0:31]
M_wrBurst
M_rdBurst
0
10000004
1111
0
0
PLB_MaddrAck
PLB_MSsize[0:1]
PLB_MRearbitrate
PLB_MBusy
PLB_RdDBus[0:31]
PLB_MRdDAck
PLB_MWrDAck
PLB_MWrErr
PLB_MRdErr
PLB_RdBTerm
PLB_WrBTerm
00
RD0
00
RD1
IP2Bus_MstRd_Req
IP2Bus_MstWr_Req
IP2Bus_Mst_Type
IP2Bus_Mst_Addr[0:31]
IP2Bus_Mst_BE[0:3]
IP2Bus_Mst_Length[0:11]
IP2Bus_Mst_Lock
IP2Bus_Mst_Reset
10000002
0011
XXX
10000004
1111
XXX
Bus2IP_Mst_CmdAck
Bus2IP_Mst_Cmplt
Bus2IP_Mst_Error
Bus2IP_Mst_Rearbitrate
Bus2IP_Mst_Cmd_Timeout
Bus2IP_MstRd_d[0:31]
RD0
RD1
Bus2IP_MstRd_REM[0:3]
0011
1111
Bus2IP_MstRd_sof_n
Bus2IP_MstRd_eof_n
Bus2IP_MstRd_src_rdy_n
Bus2IP_MstRd_src_dsc_n
IP2Bus_MstRd_dst_rdy_n
IP2Bus_MstRd_dst_dsc_n
IP2Bus_MstWr_d[0:31]
IP2Bus_MstWr_REM[0:3]
IP2Bus_MstWr_sof_n
IP2Bus_MstWr_eof_n
IP2Bus_MstWr_src_rdy_n
IP2Bus_MstWr_src_dsc_n
Bus2IP_MstWr_dst_rdy_n
Bus2IP_MstWr_dst_dsc_n
Figure 3: PLB Single Data Beat Read Timing
DS565 December 14, 2010
www.xilinx.com
11
Product Specification