DS565 Datasheet, PDF (2/28 Pages) Xilinx, Inc – PLBV46 Master Burst

PLBV46 Master Burst (v1.01a)
Functional Description
The PLBV46 Master Burst is designed to provide a User with a quick way to implement a mastering interface
between User logic and the IBM PLB V4.6. Figure 1 shows a block diagram of the PLBV46 Master Burst. The port
references and groupings are detailed in Table 1. The design allows for parameterization of both the Master’s
internal data width (Native Data Width) and the PLB data width of 32, 64, or 128 bits. Transfer request protocol
between the PLB and the User Logic is provided by the Read and Write Controller block. The Bus Width Adapter
and Steering Logic block provides the necessary function to connect the Master’s internal logic to the three available
PLB widths; 32, 64, and 128-bits. The PLB width must be greater than or equal to the Master’s Native Data Width.
Xilinx Local Link Interface
X-Ref Target - Figure 1
PLBV46_MASTER_BURST
User IP
Design
MPLB_Clk
MPLB_Rst
Master Request & Qualifiers
PLB Reply
Master Write Data
(32/64/128 bits)
PLB Read Data
(32/64/128 bits)
Bus Width
Adapter
and
Steering
Logic
Conv.
Cycle
And
Burst
Length
Adjust
Adptr.
Read
&
Write
Controller
IPIC
Rd/Wr Req & Qualifiers
Status Reply
Write
LocalLink
Backend
Read
LocalLink
Backend
Write LocalLink
Read LocalLink
Figure 1: PLBV46 Master Burst Block Diagram
The Client IP receives data from and transmits data to the PLB Master via the Xilinx LocalLink Interface protocol.
LocalLink is a point-to-point, synchronous interface intended for high data rate applications. Because data flow is
unidirectional, the PLB Master employs two LocalLink interfaces, one for IP Client data read operations and one for
IP Client data write operations.
LocalLink is based upon the concept of a Source device transmitting data to a Destination device. Data flow is
unidirectional; always from the Source to the Destination. Both Source and Destination can throttle transfers as well
as choose to discontinue the transfer. In order for a transfer data beat to complete., both the Source and the
Destination must signal that they are ready at the rising edge of the transfer synchronization clock (clk). The Source
indicates a ready condition by asserting the src_rdy_n signal. The Destination indicates ready by asserting the
dst_rdy_n signal.
Data (d[n:0]) is transferred in a delimited group otherwise known as a packet. The start of a packet is delimited with
the assertion of the Start-of-Frame signal (sof_n) by the Source. The assertion of End-of-Frame by the Source (eof_n)
delimits the last data beat of a packet. A single data beat transfer is delimited with simultaneous assertion of sof_n
and eof_n.
Transfer acknowledge/throttling is accomplished with the assertion of src_rdy_n and dst_rdy_n. De-assertion of
either signal will throttle the transfer. If the Destination device can no longer transfer data or no longer needs data,
DS565 December 14, 2010
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Product Specification