DS565 Datasheet, PDF (26/28 Pages) Xilinx, Inc – PLBV46 Master Burst

PLBV46 Master Burst (v1.01a)
Burst Length Expansion
Burst length Expansion is required when a Master attempts to perform a Fixed Length Burst operation where the
requested data transfer width (M_size(0:3)) is wider than the Native Data Width of the target Slave. In this case,
both the Master and the Slave must automatically adjust the number of data beats required on the PLB to transfer
the requested data quantity at the Slave’s Native Data Width per data beat.
Conversion Cycle and Burst Length Expansion Logic Inclusion
Conversion Cycle and Burst Length Expansion support logic is automatically included in the Master’s
implementation if the parameter C_MPLB_SMALLEST_SLAVE is assigned a value that is less than the assigned
value for the C_MPLB_NATIVE_DWIDTH parameter and the parameter C_INHIBIT_CC_BLE_INCLUSION is left
at the default value of 0. However, this logic is resource intensive and can significantly increase the size of the
Master and decrease its Fmax capability. If the User can guarantee that the Master will never access a target Slave in
a manner that will require Conversion Cycles or Burst Length Expansion, then the automatic inclusion of the
Conversion Cycle logic can be overridden by setting the C_INHIBIT_CC_BLE_INCLUSION parameter to a value of
1.
IP Master Bus Locking
This Master does not currently support PLB Bus Lock. User must tie the IP2Bus_Mst_Lock input port to logic low.
Design Implementation
Target Technology
The intended target technology is a Spartan or Virtex FPGA.
Device Utilization and Performance Benchmarks
Since the PLBV46 Master Burst is a module that will be used with other design modules in the FPGA, the utilization
and timing numbers reported in this section should be considered engineering estimates. As the PLBV46 Master
Burst is combined with other pieces of the User FPGA design, the utilization of FPGA resources and timing will
vary from the results reported here.
The resource utilization of this version of the PLBV46 Master Burst is shown in Table 4 for currently changeable
parameter configurations. The design resource utilization numbers are taken from the resource utilization section of
the Xilinx ISE MAP report that is created by the MAP tool. Default synthesis and implementation properties were
utilized.
DS565 December 14, 2010
www.xilinx.com
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Product Specification