DS565 Datasheet, PDF (27/28 Pages) Xilinx, Inc – PLBV46 Master Burst

PLBV46 Master Burst (v1.01a)
The PLBV46 Master Burst benchmarks are shown in the following table for a Virtex-4 xc4vlx200-11ff1513 FPGA.
Table 4: PLBV46 Master Burst FPGA Performance and Resource Utilization Benchmarks
Parameter Values⁽¹⁾
Device Resources
f_MAX(2)
Slices
Slice
Flip-Flops
4-input
LUTs
f_MAX(2)
(MHz)
128
128
32
376
194
645
150
128
128
64
376
194
645
150
128
128
128
221
122
379
231
128
64
32
306
177
505
205
128
64
64
182
111
301
239
128
32
32
161
107
263
239
64
64
32
308
177
505
205
64
64
64
182
111
301
239
64
32
32
161
107
263
239
32
32
32
161
107
263
239
Note:
1. C_MPLB_AWIDTH fixed at 32 and C_INHIBIT_CC_BLE_INCLUSION fixed at 0. The setting of
C_FAMILY is for Virtex-5 device family.
2. Fmax represents the maximum estimated frequency of the PLBV46 Master Burst in a standalone
configuration as reported by ISE XST. The actual maximum frequency will depend on the entire
system and may be greater or less than what is recorded in this table.
Specification Exceptions
The following High Level PLB features are not supported by the PLBV46 Master Burst design.
• Bus Slave
• Split Bus Transactions
• Command Abort
• Indeterminate Length Bursts
• Cachelines
• Bus Locking
DS565 December 14, 2010
www.xilinx.com
27
Product Specification