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DS923 Datasheet, PDF (6/56 Pages) Xilinx, Inc – DC and AC Switching Characteristics
Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics
Table 3: DC Characteristics Over Recommended Operating Conditions (Cont’d)
Symbol
Description
Min
Typ(1)
Max Units
Uncalibrated programmable on-die termination in I/O banks (measured per JEDEC specification)
Thevenin equivalent resistance of programmable input
termination to VCCO/2 where ODT = RTT_40.
Thevenin equivalent resistance of programmable input
termination to VCCO/2 where ODT = RTT_48.
Thevenin equivalent resistance of programmable input
termination to VCCO/2 where ODT = RTT_60.
Programmable input termination to VCCO where
R(8)
ODT = RTT_40.
Programmable input termination to VCCO where
ODT = RTT_48.
40
Ω
48
Ω
60
Ω
40
Ω
48
Ω
Programmable input termination to VCCO where
ODT = RTT_60.
60
Ω
Programmable input termination to VCCO where
ODT = RTT_120.
120
Ω
Programmable input termination to VCCO where
ODT = RTT_240.
240
Ω
Internal VREF
Differential
termination
n
r
50% VCCO
70% VCCO
Programmable differential termination (TERM_100)
for the I/O banks.
Temperature diode ideality factor.
Temperature diode series resistance.
VCCO x
0.49
VCCO x
0.50
VCCO x
0.51
V
VCCO x
0.69
VCCO x
0.70
VCCO x
0.71
V
–
100
–
Ω
–
1.026
–
–
–
–
Ω
Notes:
1. Typical values are specified at nominal voltage, 25°C.
2. For the I/O banks with a VCCO of 1.8V and separated VCCO and VCCAUX_IO power supplies, the IL maximum current is 70 µA.
3. This measurement represents the die capacitance at the pad, not including the package.
4. Maximum value specified for worst case process at 25°C.
5. IBATT is measured when the battery-backed RAM (BBRAM) is enabled.
6. If VRP resides at a different bank (DCI cascade), the range increases to ±15%.
7. VRP resistor tolerance is (240Ω ±1%)
8. On-die input termination resistance, for more information see the UltraScale Architecture SelectIO Resources User Guide
(UG571).
DS923 (v1.0) April 20, 2016
Advance Product Specification
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