DS923 Datasheet, PDF (43/56 Pages) Xilinx, Inc – DC and AC Switching Characteristics

Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics
Table 49: GTY Transceiver Transmitter Switching Characteristics (Cont’d)
Symbol
Description
Condition
Min
Typ
Max Units
T_J1.25
D_J1.25
T_J500
D_J500
Total jitter⁽³⁾⁽⁴⁾
Deterministic jitter⁽³⁾⁽⁴⁾
Total jitter⁽³⁾⁽⁴⁾
Deterministic jitter⁽³⁾⁽⁴⁾
1.25 Gb/s⁽⁸⁾
–
–
UI
–
–
UI
–
–
UI
500 Mb/s
–
–
UI
Notes:
1. Using same REFCLK input with TX phase alignment enabled for up to four consecutive transmitters (one fully populated
GTY Quad) at maximum line rate.
2. Using QPLL_FBDIV = 40, 20-bit internal data width. These values are NOT intended for protocol specific compliance
determinations.
3. Using CPLL_FBDIV = 2, 20-bit internal data width. These values are NOT intended for protocol specific compliance
determinations.
4. All jitter values are based on a bit-error ratio of 10^-12.
5. CPLL frequency at 3.2 GHz and TXOUT_DIV = 2.
6. CPLL frequency at 1.6 GHz and TXOUT_DIV = 1.
7. CPLL frequency at 2.5 GHz and TXOUT_DIV = 2.
8. CPLL frequency at 2.5 GHz and TXOUT_DIV = 4.
DS923 (v1.0) April 20, 2016
Advance Product Specification
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