DS923 Datasheet, PDF (29/56 Pages) Xilinx, Inc – DC and AC Switching Characteristics

Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics
Clock Buffers and Networks
Table 31: Clock Buffers Switching Characteristics
Symbol
Description
Speed Grade and
V_CCINT Operating Voltages
0.90V
0.85V
0.72V
-3
-2
-1
-2
-1
Global Clock Switching Characteristics (Including BUFGCTRL)
F_MAX
Maximum frequency of a global clock tree
(BUFG).
891
775
667
725
667
Global Clock Buffer with Input Divide Capability (BUFGCE_DIV)
F_MAX
Maximum frequency of a global clock buffer with
input divide capability (BUFGCE_DIV).
891
775
667
725
667
Global Clock Buffer with Clock Enable (BUFGCE)
F_MAX
Maximum frequency of a global clock buffer with
clock enable (BUFGCE).
891
775
667
725
667
Leaf Clock Buffer with Clock Enable (BUFCE_LEAF)
F_MAX
Maximum frequency of a leaf clock buffer with
clock enable (BUFCE_LEAF).
891
775
667
725
667
GTY Clock Buffer with Clock Enable and Clock Input Divide Capability (BUFG_GT)
Maximum frequency of a serial transceiver clock
F_MAX
buffer with clock enable and clock input divide
512
512
512
512
512
capability.
Units
MHz
MHz
MHz
MHz
MHz
MMCM Switching Characteristics
Table 32: MMCM Specification
Symbol
Description
Speed Grade and
V_CCINT Operating Voltages
0.90V
0.85V
0.72V
Units
-3
-2
-1
-2
-1
MMCM_F_INMAX
MMCM_F_INMIN
MMCM_F_INJITTER
Maximum input clock frequency.
Minimum input clock frequency.
Maximum input clock period jitter.
Input duty cycle range: 10–49 MHz.
1066
933
800
933
800 MHz
10
10
10
10
10
MHz
< 20% of clock input period or 1 ns Max
25–75
%
Input duty cycle range: 50–199 MHz.
30–70
%
MMCM_F_INDUTY
Input duty cycle range: 200–399 MHz.
35–65
%
Input duty cycle range: 400–499 MHz.
40–60
%
Input duty cycle range: >500 MHz.
45–55
%
MMCM_F_{MIN_PSCLK}
Minimum dynamic phase shift clock
frequency.
0.01
0.01
0.01
0.01
0.01 MHz
MMCM_F_{MAX_PSCLK}
Maximum dynamic phase shift clock
frequency.
550
500
450
500
450 MHz
MMCM_F_VCOMIN
MMCM_F_VCOMAX
Minimum MMCM VCO frequency.
Maximum MMCM VCO frequency.
800
1600
800
1600
800
1600
800
1600
800
1600
MHz
MHz
DS923 (v1.0) April 20, 2016
Advance Product Specification
www.xilinx.com
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