DS923 Datasheet, PDF (39/56 Pages) Xilinx, Inc – DC and AC Switching Characteristics

Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics
Table 44: GTY Transceiver Dynamic Reconfiguration Port (DRP) Switching Characteristics
Symbol
Description
All Speed Grades
Units
F_GTYDRPCLK GTYDRPCLK maximum frequency.
MHz
Table 45: GTY Transceiver Reference Clock Switching Characteristics
Symbol
Description
Conditions
All Speed Grades
Min
Typ
Max
F_GCLK
T_RCLK
T_FCLK
T_DCREF
Reference clock frequency range.
60
Reference clock rise time.
20% – 80%
–
Reference clock fall time.
80% – 20%
–
Reference clock duty cycle.
Transceiver PLL only
40
–
820
200
–
200
–
50
60
Units
MHz
ps
ps
%
X-Ref Target - Figure 5
80%
T_RCLK
20%
T_FCLK
ds923_05_041816
Figure 5: Reference Clock Timing Parameters
Table 46: GTY Transceiver Reference Clock Oscillator Selection Phase Noise Mask⁽¹⁾
Symbol
Description
Offset
Frequency
Min
Typ
Max
QPLL0/QPLL1 reference clock select
10 kHz
–
–
–112
phase noise mask at
100 kHz
–
–
–128
REFCLK frequency = 156.25 MHz.
1 MHz
–
–
–145
QPLL0/QPLL1 reference clock select
10 kHz
–
–
–103
QPLL_REFCLKMASK
phase noise mask at
REFCLK frequency = 312.5 MHz.
100 kHz
–
–
–123
1 MHz
–
–
–143
QPLL0/QPLL1 reference clock select
10 kHz
–
–
–98
phase noise mask at
100 kHz
–
–
–117
REFCLK frequency =625 MHz.
1 MHz
–
–
–140
Units
dBc/Hz
dBc/Hz
dBc/Hz
DS923 (v1.0) April 20, 2016
Advance Product Specification
www.xilinx.com
Send Feedback
39