DS923 Datasheet, PDF (13/56 Pages) Xilinx, Inc – DC and AC Switching Characteristics

Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics
Table 13: DC Output Levels for Single-ended and Differential POD10 and POD12 Standards⁽¹⁾⁽²⁾
Symbol
R_OL
R_OH
Description
Pull-down resistance.
Pull-up resistance.
V_OUT
V_{OM_DC} (as described in Table 14)
V_{OM_DC} (as described in Table 14)
Min
36
36
Typ
40
40
Max
44
44
Units
Ω
Ω
Notes:
1. Tested according to relevant specifications.
2. Standards specified using the default I/O standard configuration. For details, see the UltraScale Architecture
SelectIO Resources User Guide (UG571).
Table 14: Table 13 Definitions for DC Output Levels for POD Standards
Symbol
Description
All Speed Grades
V_{OM_DC}
DC output Mid measurement level (for IV curve linearity).
0.8 x V_CCO
Units
V
LVDS DC Specifications (LVDS)
Table 15: LVDS DC Specifications
Symbol
DC Parameter
Conditions
Min Typ Max Units
V_CCO(1)
V_ODIFF(2)
Supply voltage.
Differential output voltage:
(Q – Q), Q = High
(Q – Q), Q = High
1.710 1.800 1.890 V
R_T = 100Ω across Q and Q signals 247 350 600
mV
V_OCM(2)
V_IDIFF
Output common-mode voltage.
Differential input voltage:
(Q – Q), Q = High
(Q – Q), Q = High
R_T = 100 Ω across Q and Q signals 1.000 1.250 1.425
V
100 350 600⁽³⁾ mV
V_{ICM_DC(4)}
V_{ICM_AC(5)}
Input common-mode voltage (DC coupling).
Input common-mode voltage (AC coupling).
0.300 1.200 1.425 V
0.600 – 1.100 V
Notes:
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for the V_IN I/O pin voltage.
2. V_OCM and V_ODIFF values are for LVDS_PRE_EMPHASIS = FALSE.
3.
Maximum
when the
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4. Input common mode voltage for DC coupled configurations. EQUALIZATION = EQ_NONE (Default).
5. External input common mode voltage specification for AC coupled configurations. EQUALIZATION = EQ_LEVEL0,
EQ_LEVEL1, EQ_LEVEL2, EQ_LEVEL3, EQ_LEVEL4.
DS923 (v1.0) April 20, 2016
Advance Product Specification
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