DS923 Datasheet, PDF (40/56 Pages) Xilinx, Inc – DC and AC Switching Characteristics

Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics
Table 46: GTY Transceiver Reference Clock Oscillator Selection Phase Noise Mask⁽¹⁾ (Cont’d)
Symbol
Description
Offset
Frequency
Min
Typ
Max
Units
10 kHz
–
–
–112
CPLL reference clock select phase noise _{100 kHz}
–
–
–128
mask at REFCLK
dBc/Hz
frequency = 156.25 MHz.
1 MHz
–
–
–145
50 MHz
–
–
–145
10 kHz
–
–
–103
CPLL_REFCLKMASK
CPLL reference clock select phase noise ^{100 kHz}
mask at REFCLK frequency = 312.5 MHz. _{1 MHz}
–
–
–
–123
dBc/Hz
–
–143
50 MHz
–
–
–145
10 kHz
–
–
–98
CPLL reference clock select phase noise ^{100 kHz}
mask at REFCLK frequency = 625 MHz. _{1 MHz}
–
–
–
–117
dBc/Hz
–
–140
50 MHz
–
–
–144
Notes:
1. For reference clock frequencies not in this table, use the phase-noise mask for the nearest reference clock frequency.
Table 47: GTY Transceiver PLL/Lock Time Adaptation
Symbol
Description
Conditions
T_LOCK
T_DLOCK
Initial PLL lock.
Clock recovery phase acquisition and
adaptation time for decision
feedback equalizer (DFE).
Clock recovery phase acquisition and
adaptation time for low-power mode
(LPM) when the DFE is disabled.
After the PLL is locked to
the reference clock, this is
the time it takes to lock
the clock data recovery
(CDR) to the data present
at the input.
All Speed Grades
Min
Typ
Max
–
–
1
–
–
Units
ms
UI
UI
DS923 (v1.0) April 20, 2016
Advance Product Specification
www.xilinx.com
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