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DS923 Datasheet, PDF (17/56 Pages) Xilinx, Inc – DC and AC Switching Characteristics
Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics
FPGA Logic Performance Characteristics
This section provides the performance characteristics of some common functions and designs
implemented in Virtex UltraScale+ FPGAs. These values are subject to the same guidelines as the AC
Switching Characteristics, page 14.
Table 19: LVDS Component Mode Performance
Description
Speed Grade and VCCINT Operating Voltages
0.90V
0.85V
0.72V
-3
-2
-1
-2
-1
LVDS TX DDR (OSERDES 4:1, 8:1)
1250
1250
1250
1250
1250
LVDS TX SDR (OSERDES 2:1, 4:1)
710
710
625
710
625
LVDS RX DDR (ISERDES 1:4, 1:8)(1)
1250
1250
1250
1250
1250
LVDS RX SDR (ISERDES 1:2, 1:4)(1)
710
710
625
710
625
Units
Mb/s
Mb/s
Mb/s
Mb/s
Notes:
1. LVDS receivers are typically bounded with certain applications where specific dynamic phase-alignment (DPA) or
phase-tracking algorithms are used to achieve maximum performance.
Table 20: LVDS Native Mode Performance(1)
Description
Speed Grade and VCCINT Operating Voltages
0.90V
0.85V
0.72V
-3
-2
-1
-2
-1
LVDS TX DDR (TX_BITSLICE 4:1, 8:1)
1600
1600
1250
1600
1250
LVDS TX SDR (TX_BITSLICE 2:1, 4:1)
LVDS RX DDR (RX_BITSLICE 1:4, 1:8)(2)
LVDS RX SDR (RX_BITSLICE 1:2, 1:4)(2)
800
1600
800
800
1600
800
625
1250
625
800
1600
800
625
1250
625
Units
Mb/s
Mb/s
Mb/s
Mb/s
Notes:
1. Native mode is supported through the High-Speed SelectIO Interface Wizard available with the Vivado Design Suite.
2. LVDS receivers are typically bounded with certain applications where specific dynamic phase-alignment (DPA) or
phase-tracking algorithms are used to achieve maximum performance.
Table 21: LVDS Native-Mode 1000BASE-X Support(1)
Description
Speed Grade and VCCINT Operating Voltages
0.90V
0.85V
0.72V
-3
-2
-1
-2
-1
1000BASE-X
Yes
Notes:
1. 1000BASE-X support is based on the IEEE Standard for CSMA/CD Access Method and Physical Layer Specifications (IEEE
Std 802.3-2008).
DS923 (v1.0) April 20, 2016
Advance Product Specification
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