DS923 Datasheet, PDF (31/56 Pages) Xilinx, Inc – DC and AC Switching Characteristics

Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics
PLL Switching Characteristics
Table 33: PLL Specification⁽¹⁾
Symbol
Description
Speed Grade and
V_CCINT Operating Voltages
0.90V
0.85V
0.72V
Units
-3
-2
-1
-2
-1
PLL_F_INMAX
PLL_F_INMIN
PLL_F_INJITTER
Maximum input clock frequency.
Minimum input clock frequency.
Maximum input clock period jitter.
Input duty cycle range: 70–399 MHz.
1066
933
800
933
800 MHz
70
70
70
70
70
MHz
< 20% of clock input period or 1 ns Max
35–65
%
PLL_F_INDUTY
Input duty cycle range: 400–499 MHz.
40–60
%
Input duty cycle range: >500 MHz.
45–55
%
PLL_F_VCOMIN
PLL_F_VCOMAX
PLL_T_{STATPHAOFFSET}
PLL_T_OUTJITTER
PLL_T_OUTDUTY
Minimum PLL VCO frequency.
Maximum PLL VCO frequency.
Static phase offset of the PLL outputs.⁽²⁾
PLL output jitter.
PLL CLKOUT0, CLKOUT0B, CLKOUT1,
CLKOUT1B duty-cycle precision.⁽⁴⁾
750
1500
0.12
0.165
750
1500
0.12
0.20
750
750
1500 1500
0.12
0.12
Note 3
0.20
0.20
750
1500
0.12
MHz
MHz
ns
0.20
ns
PLL_T_LOCKMAX
PLL_F_OUTMAX
PLL maximum lock time.
PLL maximum output frequency at
CLKOUT0, CLKOUT0B, CLKOUT1,
CLKOUT1B.
PLL maximum output frequency at
CLKOUTPHY.
100
µs
891
775
667
725
667 MHz
2667 2667 2400 2400 2133 MHz
PLL_F_OUTMIN
PLL minimum output frequency at
CLKOUT0, CLKOUT0B, CLKOUT1,
CLKOUT1B.⁽⁵⁾
PLL minimum output frequency at
CLKOUTPHY.
5.86
5.86
5.86
5.86
5.86 MHz
2 x VCO mode: 1500, 1 x VCO mode: 750
0.5 x VCO mode: 375
MHz
PLL_RST_MINPULSE
PLL_F_PFDMAX
Minimum reset pulse width.
Maximum frequency at the phase
frequency detector.
5.00
667.5
5.00
667.5
5.00
667.5
5.00
667.5
5.00
667.5
ns
MHz
PLL_F_PFDMIN
Minimum frequency at the phase
frequency detector.
70
70
70
70
70
MHz
PLL_F_BANDWIDTH
PLL bandwidth at typical.
14
14
14
14
14
MHz
Notes:
1. The PLL does not filter typical spread-spectrum input clocks because they are usually far below the loop filter frequencies.
2. The static offset is measured between any PLL outputs with identical phase.
3. Values for this parameter are available in the Clocking Wizard.
4. Includes global clock buffer.
5. Calculated as F_VCO/128 assuming output duty cycle is 50%.
DS923 (v1.0) April 20, 2016
Advance Product Specification
www.xilinx.com
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