DS923 Datasheet, PDF (32/56 Pages) Xilinx, Inc – DC and AC Switching Characteristics

Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics
Device Pin-to-Pin Output Parameter Guidelines
The pin-to-pin numbers in Table 34 through Table 36 are based on the clock root placement in the center
of the device. The actual pin-to-pin values will vary if the root placement selected is different. Consult the
Vivado Design Suite timing report for the actual pin-to-pin values.
Table 34: Global Clock Input to Output Delay Without MMCM (Near Clock Region)
Symbol
Description
Device
Speed Grade and
V_CCINT Operating Voltages
0.90V
0.85V
0.72V
Units
-3
-2
-1
-2
-1
SSTL15 Global Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, without MMCM.
T_ICKOF
Global clock input and output
XCVU3P
4.72
5.28
5.65
5.93
6.40
ns
flip-flop without MMCM (near clock
region).
XCVU5P
4.72
5.28
5.65
5.93
6.40
ns
XCVU7P
4.72
5.28
5.65
5.93
6.40
ns
XCVU9P
4.72
5.28
5.65
5.93
6.40
ns
XCVU11P 4.78
5.31
5.66
5.95
6.48
ns
XCVU13P 4.78
5.31
5.66
5.95
6.48
ns
Notes:
1. This table lists representative values where one global clock input drives one vertical clock line in each accessible column,
and where all accessible I/O and CLB flip-flops are clocked by the global clock net in a single SLR.
Table 35: Global Clock Input to Output Delay Without MMCM (Far Clock Region)
Symbol
Description
Device
Speed Grade and
V_CCINT Operating Voltages
0.90V
0.85V
0.72V
Units
-3
-2
-1
-2
-1
SSTL15 Global Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, without MMCM.
T_{ICKOF_FAR}
Global clock input and output
XCVU3P 5.23
5.90
6.35
6.73
7.34
ns
flip-flop without MMCM (far clock
region).
XCVU5P
5.23
5.90
6.35
6.73
7.34
ns
XCVU7P 5.23
5.90
6.35
6.73
7.34
ns
XCVU9P 5.23
5.90
6.35
6.73
7.34
ns
XCVU11P 4.96
5.51
5.87
6.21
6.77
ns
XCVU13P 4.96
5.51
5.87
6.21
6.77
ns
Notes:
1. This table lists representative values where one global clock input drives one vertical clock line in each accessible column,
and where all accessible I/O and CLB flip-flops are clocked by the global clock net in a single SLR.
DS923 (v1.0) April 20, 2016
Advance Product Specification
www.xilinx.com
Send Feedback
32