DS923 Datasheet, PDF (27/56 Pages) Xilinx, Inc – DC and AC Switching Characteristics

Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics
Block RAM and FIFO Switching Characteristics
Table 27: Block RAM and FIFO Switching Characteristics
Symbol
Description
Speed Grade and
V_CCINT Operating Voltages
0.90V
0.85V
0.72V
-3
-2
-1
-2
-1
Maximum Frequency
F_{MAX_WF_NC}
Block RAM
(WRITE_FIRST and NO_CHANGE modes).
825
737
645
585
516
F_{MAX_RF}
Block RAM (READ_FIRST mode).
718
637
575
510
460
F_{MAX_FIFO}
FIFO in all modes without ECC.
825
737
645
585
516
Block RAM and FIFO in ECC configuration
without PIPELINE.
718
637
575
510
460
F_{MAX_ECC}
Block RAM and FIFO in ECC configuration with
PIPELINE and Block RAM in WRITE_FIRST or 825
737
645
585
516
NO_CHANGE mode.
T_PW(1)
Minimum pulse width.
Block RAM and FIFO Clock-to-Out Delays
495
542
543
577
578
T_{RCKO_DO}
Clock CLK to DOUT output (without output
register).
0.92
1.03
1.11
1.46
1.54
T_{RCKO_DO_REG}
Clock CLK to DOUT output (with output
register).
0.27
0.29
0.31
0.42
0.44
Units
MHz
MHz
MHz
MHz
MHz
ps
ns,
Max
ns,
Max
Notes:
1. The MMCM and PLL DUTY_CYCLE attribute should be set to 50% to meet the pulse-width requirements at the higher
frequencies.
UltraRAM Switching Characteristics
Table 28: UltraRAM Switching Characteristics
Symbol
Description
Maximum Frequency
F_MAX
UltraRAM maximum frequency with
OREG_B.
F_{MAX_ECC}
UltraRAM maximum frequency without
OREG_B and EN_ECC_RD_B = True.
UltraRAM maximum frequency with
F_{MAX_NORPIPELINE} OREG_B = False and
EN_ECC_RD_B = False.
T_PW(1)
T_RSTPW
Minimum pulse width.
Asynchronous reset minimum pulse
width.
Speed Grade and
V_CCINT Operating Voltages
0.90V
0.85V
0.72V
-3
-2
-1
-2
-1
Units
650
600
600
500
500
MHz
450
400
400
325
325
MHz
550
500
500
425
425
MHz
650
700
700
800
800
ps
550
600
600
650
650
ps
Notes:
1. The MMCM and PLL DUTY_CYCLE attribute should be set to 50% to meet the pulse-width requirements at the higher
frequencies.
DS923 (v1.0) April 20, 2016
Advance Product Specification
www.xilinx.com
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