DS923 Datasheet, PDF (23/56 Pages) Xilinx, Inc – DC and AC Switching Characteristics

Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics
Table 23: IOB High Performance (HP) Switching Characteristics (Cont’d)
I/O Standards
T_{INBUF_DELAY_PAD_I}
0.90V 0.85V
0.72V
T_{OUTBUF_DELAY_O_PAD}
0.90V 0.85V
0.72V
T_{OUTBUF_DELAY_TD_PAD}
0.90V 0.85V
0.72V
Units
-3 -2 -1 -2 -1 -3 -2 -1 -2 -1 -3 -2 -1 -2 -1
SSTL135_M
0.331 0.352 0.373 0.352 0.356 0.565 0.599 0.633 0.598 0.593 0.565 0.599 0.633 0.598 0.593 ns
SSTL135_S
0.331 0.352 0.373 0.352 0.356 0.789 0.850 0.907 0.849 0.841 0.789 0.850 0.907 0.849 0.841 ns
SSTL15_DCI_F
0.332 0.349 0.362 0.349 0.346 0.424 0.421 0.439 0.423 0.422 0.424 0.421 0.439 0.423 0.422 ns
SSTL15_DCI_M
0.332 0.349 0.362 0.349 0.346 0.591 0.632 0.667 0.632 0.627 0.591 0.632 0.667 0.632 0.627 ns
SSTL15_DCI_S
0.332 0.349 0.362 0.349 0.346 0.816 0.906 0.971 0.906 0.898 0.816 0.906 0.971 0.906 0.898 ns
SSTL15_F
0.32 0.356 0.385 0.356 0.353 0.393 0.392 0.412 0.392 0.386 0.393 0.392 0.412 0.392 0.386 ns
SSTL15_M
0.32 0.356 0.385 0.356 0.353 0.564 0.598 0.633 0.598 0.592 0.564 0.598 0.633 0.598 0.592 ns
SSTL15_S
0.32 0.356 0.385 0.356 0.353 0.790 0.853 0.910 0.85 0.844 0.790 0.853 0.910 0.85 0.844 ns
SSTL18_I_DCI_F
0.333 0.353 0.360 0.353 0.347 0.418 0.425 0.440 0.424 0.416 0.418 0.425 0.440 0.424 0.416 ns
SSTL18_I_DCI_M
0.333 0.353 0.360 0.353 0.347 0.593 0.633 0.670 0.634 0.629 0.593 0.633 0.670 0.634 0.629 ns
SSTL18_I_DCI_S
0.333 0.353 0.360 0.353 0.347 0.821 0.910 0.978 0.911 0.903 0.821 0.910 0.978 0.911 0.903 ns
SSTL18_I_F
0.323 0.355 0.378 0.355 0.364 0.388 0.395 0.415 0.392 0.387 0.388 0.395 0.415 0.392 0.387 ns
SSTL18_I_M
0.323 0.355 0.378 0.355 0.364 0.567 0.603 0.638 0.603 0.596 0.567 0.603 0.638 0.603 0.596 ns
SSTL18_I_S
0.323 0.355 0.378 0.355 0.364 0.794 0.861 0.920 0.860 0.851 0.794 0.861 0.920 0.860 0.851 ns
SUB_LVDS
0.315 0.352 0.406 0.352 0.348 0.387 0.398 0.418 0.398 0.390 0.387 0.398 0.418 0.398 0.390 ns
Table 24 specifies the values of T_{OUTBUF_DELAY_TE_PAD} and T_{INBUF_DELAY_IBUFDIS_O}. T_{OUTBUF_DELAY_TE_PAD} is the
delay from the T pin to the IOB pad through the output buffer of an IOB pad, when 3-state is enabled (i.e.,
a high impedance state). T_{INBUF_DELAY_IBUFDIS_O} is the IOB delay from IBUFDISABLE to O output. In HP I/O
banks, the internal DCI termination turn-off time is always faster than T_{OUTBUF_DELAY_TE_PAD} when the
DCITERMDISABLE pin is used.
Table 24: IOB 3-state Output Switching Characteristics
Symbol
Description
Speed Grade and
V_CCINT Operating Voltages
0.90V
0.85V
0.72V
-3
-2
-1
-2
-1
T_{OUTBUF_DELAY_TE_PAD}
T input to pad high-impedance for
the I/O banks
IBUF turn-on time from
T_{INBUF_DELAY_IBUFDIS_O} IBUFDISABLE to O output for the
I/O banks
Units
ns
ns
I/O Standard Adjustment Measurement Methodology
Input Delay Measurements
Table 25 shows the test setup parameters used for measuring input delay.
DS923 (v1.0) April 20, 2016
Advance Product Specification
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