DS923 Datasheet, PDF (34/56 Pages) Xilinx, Inc – DC and AC Switching Characteristics

Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics
Device Pin-to-Pin Input Parameter Guidelines
The pin-to-pin numbers in Table 37 are based on the clock root placement in the center of the device. The
actual pin-to-pin values will vary if the root placement selected is different. Consult the Vivado Design
Suite timing report for the actual pin-to-pin values.
Table 37: Global Clock Input Setup and Hold With MMCM
Symbol
Description
Device
Speed Grade and
V_CCINT Operating Voltages
0.90V
0.85V
0.72V
Units
-3
-2
-1
-2
-1
Input Setup and Hold Time Relative to Global Clock Input Signal using SSTL15 Standard.^(1)(2)(3)
T_{PSMMCMCC_VU3P}
T_{PHMMCMCC_VU3P}
Setup
1.82
2.14
2.34
2.34
2.34
ns
XCVU3P
Hold
0.35
0.35
0.35
0.43
0.43
ns
T_{PSMMCMCC_VU5P}
T_{PHMMCMCC_VU5P}
Setup
1.82
2.14
2.34
2.34
2.34
ns
XCVU5P
Hold
0.35
0.35
0.35
0.43
0.43
ns
T_{PSMMCMCC_VU7P}
T_{PHMMCMCC_VU7P}
Setup
Global clock input and
XCVU7P
Hold
input flip-flop (or latch)
1.82
0.35
2.14
0.35
2.34
0.35
2.34
0.43
2.34
0.43
ns
ns
T_{PSMMCMCC_VU9P with MMCM.}
Setup
1.82
2.14
2.34
2.34
2.34
ns
XCVU9P
T_{PHMMCMCC_VU9P}
Hold
0.35
0.35
0.35
0.43
0.43
ns
T_{PSMMCMCC_VU11P}
T_{PHMMCMCC_VU11P}
Setup
2.06
2.33
2.52
2.52
2.52
ns
XCVU11P
Hold
0.32
0.32
0.32
0.43
0.50
ns
T_{PSMMCMCC_VU13P}
T_{PHMMCMCC_VU13P}
Setup
2.06
2.33
2.52
2.52
2.52
ns
XCVU13P
Hold
0.32
0.32
0.32
0.43
0.50
ns
Notes:
1. Setup and hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured
relative to the global clock input signal using the slowest process, slowest temperature, and slowest voltage. Hold time is
measured relative to the global clock input signal using the fastest process, fastest temperature, and fastest voltage.
2. This table lists representative values where one global clock input drives one vertical clock line in each accessible column,
and where all accessible I/O and CLB flip-flops are clocked by the global clock net in a single SLR.
3. Use IBIS to determine any duty-cycle distortion incurred using various standards.
Table 38: Sampling Window
Description
0.90V
Speed Grade and V_CCINT Operating Voltages
0.85V
0.72V
Units
-3
-2
-1
-2
-1
T_{SAMP_BUFG(1)}
ps
T_{SAMP_NATIVE_DPA}
ps
T_{SAMP_NATIVE_BISC}
ps
Notes:
1. This parameter indicates the total sampling error of the Virtex UltraScale+ FPGA DDR input registers, measured across
voltage, temperature, and process. The characterization methodology uses the MMCM to capture the DDR input registers’
edges of operation. These measurements include: CLK0 MMCM jitter, MMCM accuracy (phase offset), and MMCM phase
shift resolution. These measurements do not include package or clock tree skew.
DS923 (v1.0) April 20, 2016
Advance Product Specification
www.xilinx.com
Send Feedback
34