DS923 Datasheet, PDF (24/56 Pages) Xilinx, Inc – DC and AC Switching Characteristics

Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics
Table 25: Input Delay Measurement Methodology
Description
I/O Standard
Attribute
V_L(1)(2)
V_H(1)(2)
(1^V)M(4E)A(S6) (1^V)(R3E)F(5)
LVCMOS, 1.2V
LVCMOS12
0.1
1.1
0.6
–
LVCMOS, LVDCI, HSLVDCI, 1.5V
LVCMOS15,
LVDCI_15,
HSLVDCI_15
0.1
1.4
0.75
–
LVCMOS, LVDCI, HSLVDCI, 1.8V
LVCMOS18,
LVDCI_18,
HSLVDCI_18
0.1
1.7
0.9
–
HSTL (high-speed transceiver logic),
class I, 1.2V
HSTL_I_12
V_REF – 0.5
V_REF + 0.5
V_REF
0.6
HSTL, class I, 1.5V
HSTL_I
HSTL, class I, 1.8V
HSTL_I_18
HSUL (high-speed unterminated logic), 1.2V HSUL_12
SSTL12 (stub series terminated logic), 1.2V SSTL12
SSTL135, 1.35V
SSTL135
SSTL15, 1.5V
SSTL15
SSTL18, class I, 1.8V
SSTL18_I
POD10, 1.0V
POD10
POD12, 1.2V
POD12
DIFF_HSTL, class I, 1.2V
DIFF_HSTL_I_12
V_REF – 0.65
V_REF – 0.8
V_REF – 0.5
V_REF – 0.5
V_REF – 0.575
V_REF – 0.65
V_REF – 0.8
V_REF – 0.6
V_REF – 0.74
0.6 – 0.125
V_REF + 0.65
V_REF + 0.8
V_REF + 0.5
V_REF + 0.5
V_REF + 0.575
V_REF + 0.65
V_REF + 0.8
V_REF + 0.6
V_REF + 0.74
0.6 + 0.125
V_REF
V_REF
V_REF
V_REF
V_REF
V_REF
V_REF
V_REF
V_REF
0⁽⁶⁾
0.75
0.9
0.6
0.6
0.675
0.75
0.9
0.7
0.84
–
DIFF_HSTL, class I, 1.5V
DIFF_HSTL, class I, 1.8V
DIFF_HSTL_I
0.75 – 0.125 0.75 + 0.125 0⁽⁶⁾
–
DIFF_HSTL_I_18
0.9 – 0.125 0.9 + 0.125
0⁽⁶⁾
–
DIFF_HSUL, 1.2V
DIFF_SSTL, 1.2V
DIFF_HSUL_12
0.6 – 0.125 0.6 + 0.125
0⁽⁶⁾
–
DIFF_SSTL12
0.6 – 0.125 0.6 + 0.125
0⁽⁶⁾
–
DIFF_SSTL135, 1.35V
DIFF_SSTL15, 1.5V
DIFF_SSTL135
0.675 – 0.125 0.675 + 0.125 0⁽⁶⁾
–
DIFF_SSTL15
0.75 – 0.125 0.75 + 0.125 0⁽⁶⁾
–
DIFF_SSTL18_I, 1.8V
DIFF_POD10, 1.0V
DIFF_POD12, 1.2V
DIFF_SSTL18_I
0.9 – 0.125 0.9 + 0.125
0⁽⁶⁾
–
DIFF_POD10
0.7 – 0.125 0.7 + 0.125
0⁽⁶⁾
–
DIFF_POD12
0.84 – 0.125 0.84 + 0.125 0⁽⁶⁾
–
LVDS (low-voltage differential signaling),
1.8V
LVDS
0.9 – 0.125 0.9 + 0.125
0⁽⁶⁾
–
SUB_LVDS, 1.8V
SUB_LVDS
0.9 – 0.125 0.9 + 0.125
0⁽⁶⁾
–
SLVS, 1.8V
SLVS_400_18
0.9 – 0.125 0.9 + 0.125
0⁽⁶⁾
–
MIPI D-PHY (high speed) 1.2V
MIPI_DPHY_DCI_HS 0.2 – 0.125 0.2 + 0.125
0⁽⁶⁾
–
MIPI D-PHY (low power) 1.2V
MIPI_DPHY_DCI_LP 0.715 – 0.2 0.715 + 0.2
0⁽⁶⁾
–
Notes:
1. The input delay measurement methodology parameters for LVDCI/HSLVDCI are the same for LVCMOS standards of the
same voltage. Parameters for all other DCI standards are the same for the corresponding non-DCI standards.
2. Input waveform switches between V_Land V_H.
3.
Measurements are made at
measurements. V_REF values
typical, minimum,
listed are typical.
and
maximum
V_REF
values.
Reported
delays
reflect
worst
case
of
these
4. Input voltage level from which measurement starts.
5.
This is an input
in Figure 1.
voltage
reference
that
bears
no
relation
to
the
V_REF/V_MEAS
parameters
found
in
IBIS
models
and/or
noted
6. The value given is the differential input voltage.
DS923 (v1.0) April 20, 2016
Advance Product Specification
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