DS923 Datasheet, PDF (11/56 Pages) Xilinx, Inc – DC and AC Switching Characteristics

Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics
DC Input and Output Levels
Values for V_IL and V_IH are recommended input voltages. Values for I_OL and I_OH are guaranteed over the
recommended operating conditions at the V_OL and V_OH test points. Only selected standards are tested.
These are chosen to ensure that all standards meet their specifications. The selected standards are tested
at a minimum V_CCO with the respective V_OL and V_OH voltage levels shown. Other standards are sample
tested.
Table 8: SelectIO DC Input and Output Levels for the I/O Banks^(1)(2)(3)
I/O
Standard
V_IL
V, Min V, Max
V_IH
V, Min
V, Max
V_OL
V, Max
V_OH
V, Min
I_OL
mA
I_OH
mA
HSTL_I
HSTL_I_12
HSTL_I_18
HSUL_12
LVCMOS12
LVCMOS15
LVCMOS18
LVDCI_15
LVDCI_18
SSTL12
SSTL135
SSTL15
SSTL18_I
MIPI_DPHY_
DCI_LP⁽⁶⁾
–0.300
–0.300
–0.300
–0.300
–0.300
–0.300
–0.300
–0.300
–0.300
–0.300
–0.300
–0.300
–0.300
V_REF – 0.100 V_REF + 0.100
V_REF – 0.080 V_REF + 0.080
V_REF – 0.100 V_REF + 0.100
V_REF – 0.130 V_REF + 0.130
35% V_CCO
65% V_CCO
35% V_CCO
65% V_CCO
35% V_CCO
65% V_CCO
35% V_CCO
65% V_CCO
35% V_CCO
65% V_CCO
V_REF – 0.100 V_REF + 0.100
V_REF – 0.090 V_REF + 0.090
V_REF – 0.100 V_REF + 0.100
V_REF – 0.125 V_REF + 0.125
V_CCO + 0.300
V_CCO + 0.300
V_CCO + 0.300
V_CCO + 0.300
V_CCO + 0.300
V_CCO + 0.300
V_CCO + 0.300
V_CCO + 0.300
V_CCO + 0.300
V_CCO + 0.300
V_CCO + 0.300
V_CCO + 0.300
V_CCO + 0.300
0.400
25% V_CCO
0.400
20% V_CCO
0.400
0.450
0.450
0.450
0.450
V_CCO/2 – 0.150
V_CCO/2 – 0.150
V_CCO/2 – 0.175
V_CCO/2 – 0.470
V_CCO – 0.400
75% V_CCO
V_CCO – 0.400
80% V_CCO
V_CCO – 0.400
V_CCO – 0.450
V_CCO – 0.450
V_CCO – 0.450
V_CCO – 0.450
V_CCO/2 + 0.150
V_CCO/2 + 0.150
V_CCO/2 + 0.175
V_CCO/2 + 0.470
5.8
4.1
6.2
0.1
Note 4
Note 5
Note 5
7.0
7.0
8.0
9.0
10.0
7.0
–5.8
–4.1
–6.2
–0.1
Note 4
Note 5
Note 5
–7.0
–7.0
–8.0
–9.0
–10.0
–7.0
–0.300
0.550
0.880
V_CCO + 0.300
0.050
1.100
0.01 –0.01
Notes:
1. Tested according to relevant specifications.
2. Standards specified using the default I/O standard configuration. For details, see the UltraScale Architecture
SelectIO Resources User Guide (UG571).
3. POD10 and POD12 DC input and output levels are shown in Table 9, Table 13, and Table 14.
4. Supported drive strengths of 2, 4, 6, or 8 mA in the I/O banks.
5. Supported drive strengths of 2, 4, 6, 8, or 12 mA in the I/O banks.
6. Low-power option for MIPI_DPHY_DCI.
Table 9: DC Input Levels for Single-ended POD10 and POD12 I/O Standards⁽¹⁾⁽²⁾
I/O
Standard
V_IL
V, Min
V, Max
V_IH
V, Min
V, Max
POD10
POD12
–0.300
–0.300
V_REF – 0.068
V_REF – 0.068
V_REF + 0.068
V_REF + 0.068
V_CCO + 0.300
V_CCO + 0.300
Notes:
1. Tested according to relevant specifications.
2. Standards specified using the default I/O standard configuration. For details, see the UltraScale Architecture
SelectIO Resources User Guide (UG571).
DS923 (v1.0) April 20, 2016
Advance Product Specification
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