DS923 Datasheet, PDF (18/56 Pages) Xilinx, Inc – DC and AC Switching Characteristics

Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics
Table 22 provides the maximum data rates for applicable memory standards using the Virtex UltraScale+
FPGA memory PHY. Refer to Memory Interfaces for the complete list of memory interface standards
supported and detailed specifications. The final performance of the memory interface is determined
through a complete design implemented in the Vivado Design Suite, following guidelines in the UltraScale
Architecture PCB Design Guide (UG583), electrical analysis, and characterization of the system.
Table 22: Maximum Physical Interface (PHY) Rate for Memory Interfaces
Memory
Standard
DRAM Type
DDR4
DDR3
DDR3L
QDR II+
RLDRAM 3
QDR IV XP
LPDDR3
Single rank component
1 rank DIMM⁽¹⁾⁽²⁾
2 rank DIMM⁽¹⁾⁽³⁾
4 rank DIMM⁽¹⁾⁽⁴⁾
Single rank component
1 rank DIMM⁽¹⁾⁽²⁾
2 rank DIMM⁽¹⁾⁽³⁾
4 rank DIMM⁽¹⁾⁽⁴⁾
Single rank component
1 rank DIMM⁽¹⁾⁽²⁾
2 rank DIMM⁽¹⁾⁽³⁾
4 rank DIMM⁽¹⁾⁽⁴⁾
Single rank component⁽⁵⁾
Single rank component
Single rank component⁽⁶⁾
Single rank component
Speed Grade and V_CCINT Operating Voltages
0.90V
0.85V
0.72V
-3
-2
-1
-2
-1
2666
2666
2400
2400
2133
2400
2400
2133
2133
1866
2133
2133
1866
1866
1600
1600
1600
1333
1333
N/A
2133
2133
2133
2133
1866
1866
1866
1866
1866
1600
1600
1600
1600
1600
1333
1066
1066
1066
1066
800
1866
1866
1866
1866
1600
1600
1600
1600
1600
1333
1333
1333
1333
1333
1066
800
800
800
800
606
633
633
600
600
550
1200
1200
1066
1066
933
1066
1066
1066
933
933
1600
1600
1600
1600
1600
Notes:
1. Dual in-line memory module (DIMM) includes RDIMM, SODIMM, UDIMM, and LRDIMM.
2. Includes: 1 rank 1 slot, DDP 2 rank, LRDIMM 2 or 4 rank 1 slot.
3. Includes: 2 rank 1 slot, 1 rank 2 slot, LRDIMM 2 rank 2 slot.
4. Includes: 2 rank 2 slot, 4 rank 1 slot.
5. The QDRII+ performance specifications are for burst-length 4 (BL = 4) implementations.
6. This memory interface is not production qualified and specification is subject to change.
Units
Mb/s
Mb/s
Mb/s
Mb/s
Mb/s
Mb/s
Mb/s
Mb/s
Mb/s
Mb/s
Mb/s
Mb/s
MHz
MHz
MHz
Mb/s
IOB Pad Input, Output, and 3-State
Table 23, high-performance IOB (HP), summarizes the values of standard-specific data input delay
adjustments, output delays terminating at pads (based on standard) and 3-state delays.
• T_{INBUF_DELAY_PAD_I} is the delay from IOB pad through the input buffer to the I-pin of an IOB pad. The
delay varies depending on the capability of the SelectIO input buffer.
• T_{OUTBUF_DELAY_O_PAD} is the delay from the O pin to the IOB pad through the output buffer of an IOB
pad. The delay varies depending on the capability of the SelectIO output buffer.
• T_{OUTBUF_DELAY_TD_PAD} is the delay from the T pin to the IOB pad through the output buffer of an IOB
pad, when 3-state is disabled. The delay varies depending on the SelectIO capability of the output
buffer. In HP I/O banks, the internal DCI termination turn-on time is always faster than
T_{OUTBUF_DELAY_TD_PAD} when the DCITERMDISABLE pin is used.
DS923 (v1.0) April 20, 2016
Advance Product Specification
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