W925EP01 Datasheet, PDF (88/108 Pages) Winbond – 8-BIT CID MICROCONTROLLER

W925EP01/ W925EP01FG
The FSK demodulation function can demodulate Bell 202 and ITU-T V.23 Frequency Shift keying
(FSK) with 1200-baud rate. When the decoder receives the FSK serial data, the serial data will be
demodulated into bit FDATA with 1200-baud rate in the mean time the synchronous clock signal is
output to the bit FCLK. As the decoder receives one byte, the internal serial-to-parallel circuit sets the
bit FDR and converts the 8-bit serial data into the byte register FSKDR. The rising edge of bit FDR will
set the flag FDRF to produce CID interrupt but FDRF is cleared by software. User can get the FSK
data by reading register FSKDR or sampling the bit FDATA. The timing of FSK demodulation is shown
in Figure 6-19.
Tip/Ring
1st byte data
start
stop
start
2nd byte data
stop
start
1* 1 0 b0 b1 b2 b3 b4 b5 b6 b7 1* 1 0 b0 b1 b2 b3 b4 b5 b6 b7 1 0 b0
t_IDD
FDATA
1st byte data
start
b0 b1 b2 b3 b4 b5 b6 b7
stop
start
2nd byte data
stop
start
b0 b1 b2 b3 b4 b5 b6 b7
1/f_DCLK0
FCLK
t_CRD
t _RH
FDR
FDRF
FSKDR
* Mark bit or redundant stop bit(s), will be omitted.
+ Clear by software.
+
1st byte data
2nd byte data
Figure 6-19 Serial Data Interface Timing of FSK Demodulation
CID Input Gain Control
The CID input gain and input hysteresis are controllable by internal CID gain control registers. CIDGD
and CIDGA registers determine the 6 internal CID gain control registers. CID gain control data register
(CIDGD) presents the data bus. The lower 3 bits of CID gain control address register (CIDGA) present
the address. The rising edge of CIDGA.4 will latch the CIDGD in the corresponding internal CID gain
control register. The 6 internal CID gain control registers are addressed as following table. Setting the
6 registers as the suggestion value guarantees the CID spec.
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