W925EP01 Datasheet, PDF (69/108 Pages) Winbond – 8-BIT CID MICROCONTROLLER

W925EP01/ W925EP01FG
updated completely. Setting CHPCON register bit 0, 1 and 7 to logic-1 will result a software-reset
to reset the CPU. The software reset serves as an external reset. This in-system programming
feature makes the job easy and efficient in which the application needs to update firmware frequently.
In some applications, the in-system programming features make it possible to easily update the
system firmware without opening the chassis.
NOTE: The ISP Mode operates by supply voltage from 3.3V to 5.5V.
SFRAH, SFRAL: The objective address of on-chip Flash EPROM in the in-system programming
mode. SFRAH contains the high-order byte of address. SFRAL contains the low-
order byte of address.
SFRFD: The programming data for on-chip Flash EPROM in programming mode.
SFRCN: The control byte of on-chip Flash EPROM programming mode.
SFRCN (E7H)
BIT
NAME
FUNCTION
7
-
Reserve.
WFWIN On-chip Flash EPROM bank select for in-system programming.
= 0: 64K bytes Flash EPROM bank is selected as destination for re-
6
programming.
= 1: 4K bytes Flash EPROM bank is selected as destination for re-
programming.
5
OEN
Flash EPROM output enable.
4
CEN
Flash EPROM chip enable.
3, 2, 1, 0 CTRL[3:0] The Flash control signals
MODE
Erase 64KB APROM
Program 64KB
APROM
Read 64KB APROM
Erase 4KB LDROM
Program 4KB
LDROM
Read 4KB LDROM
WFWIN
0
0
0
1
1
1
OEN
1
1
0
1
1
0
CEN
0
0
0
0
0
0
CTRL<3:0> SFRAH, SFRAL
0010
X
0001
Address in
0000
0010
Address in
X
0001
Address in
0000
Address in
SFRFD
X
Data in
Data out
X
Data in
Data out
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Publication Release Date: Apr. 10, 2006
Revision A2