W925EP01 Datasheet, PDF (34/108 Pages) Winbond – 8-BIT CID MICROCONTROLLER

W925EP01/ W925EP01FG
restarts the crystal oscillator, the X1UP (STATUS.4) bit will be set after crystal oscillator
warmed-up has completed.
DME0: This bit determines the on-chip MOVX SRAM to be enabled or disabled. Set this bit to
1(default) will enable the on-chip 4K bytes MOVX SRAM. Clear this bit to 0 will disable the on-
chip 4K bytes MOVX SRAM.
The W925EP01 contains on-chip 4K MOVX SRAM of Data Memory, which can only be
accessed by MOVX instructions from the address 000H to FFFH. Access to the on-chip
MOVX SRAM is optional by software setting DME0, MOVX addresses greater than FFFH
automatically go to external memory through A0 to A15; this is the default condition. When
DME0 be clearing, the 4K data memory area is transparent to the system memory map. Any
MOVX directed to the space between 0000H to FFFFH goes to expanded bus on A0 to A15.
STATUS REGISTER
(initial=00H)
Bit:
7
6
5
4
3
2
1
0
X2UP
HIP
LIP
X1UP
-
-
-
-
Mnemonic: STATUS
Address: C5h
X2UP: Sub-crystal oscillator warm-up status. When set, this bit indicates the crystal oscillator has
completed the warm-up delay. When X2OFF bit is set, hardware will clear this bit. There are
two options which are selected by option code for warm-up delay, one is 1024 clocks warm-up
delay, and other is 65536 clocks warm-up delay.
HIP: High Priority Interrupt Status. When set, it indicates that software is servicing a high priority
interrupt. This bit will be cleared when the program executes the corresponding RETI instruction.
LIP: Low Priority Interrupt Status. When set, it indicates that software is servicing a low priority
interrupt. This bit will be cleared when the program executes the corresponding RETI instruction.
X1UP: Crystal Oscillator Warm-up Status. When set, this bit indicates the crystal oscillator has
completed the 65536 clocks warm-up delay. Each time the crystal oscillator is restarted by exit
from power down mode or the X1OFF bit is set, hardware will clear this bit. This bit is set to 1
after a power-on reset. When this bit is cleared, it prevents software from setting the XT/ RG bit
to enable CPU operation from crystal oscillator. There are two options which are selected by
option code for warm-up delay, one is 4096 clocks warm-up delay, and other is 65536 clocks
warm-up delay.
FSK TRANSIMT CONTROL REGISTER
(initial=00H)
Bit:
7
6
5
4
3
2
1
0
FTE FTM FDS
-
-
-
LO1 LO0
Mnemonic: FSKTC
Address: C6h
FTE: FSK transmit Enable; Enable=1, Disable=0
FTM: FSK signal Standard; Bellcore=1, V.23=0
FDS: FSK data sending status
LO0, LO1: CAS/FSK transmitting level option. In CAS tone, it just is suitable for 2130Hz. The output
levels of 2750Hz will higher 2dBm than it.
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