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W925EP01 Datasheet, PDF (46/108 Pages) Winbond – 8-BIT CID MICROCONTROLLER
W925EP01/ W925EP01FG
Power down Mode
The device can be put into Power Down mode by writing 1 to bit PCON.1. The instruction that does
this will be the last instruction to be executed before the device goes into Power Down mode. In the
Power Down mode, all the clocks are stopped and the device comes to a halt. All activity is completely
stopped and the power consumption is reduced to the lowest possible value. The port pins output the
values held by their respective SFRs.
The W925EP01 will exit the Power Down mode by reset or external interrupts or ring detected. An
external reset can be used to exit the Power down state. The low on RESET pin terminates the Power
Down mode, and restarts the clock. The on-chip hardware will now provide a delay of 65536 clocks,
which is used to provide time for the oscillator to restart and stabilize. Once this delay is complete, an
internal reset is activated and the program execution will restart from 0000h. In the Power down mode,
the clock is stopped, so the Watchdog timer cannot be used to provide the reset to exit Power down
mode.
The W925EP01 can be woken from the Power Down mode by forcing an external interrupt pin
activated and ring detected, provided the corresponding interrupt is enabled, while the global enable
(EA) bit is set. While the power down is released, the device will experience a warm-up delay of 65536
clock cycles to ensure the stabilization of oscillation. Then device executes the interrupt service
routine for the corresponding external interrupt or CID interrupt. After the interrupt service routine is
completed, the program returns to the instruction after the one, which put the device into Power Down
mode and continues from there. When RGSL (PMR.5) bit is set to 1, the CPU will use the internal RC
oscillator instead of crystal to exit Power Down mode. The micro-controller will automatically switch
from RC oscillator to crystal after a warm-up delay of 65536 crystal clocks. The RC oscillator runs at
approximately 2−4 MHz. Using RC oscillator to exit from Power Down mode saves the time for waiting
crystal start-up. It is useful in the low power system which usually be awakened from a short operation
then returns to Power Down mode.
6.6 Reset
The user has several hardware related options for placing the W925EP01 into reset condition. In
general, most register bits go to their reset value irrespective of the reset condition, but there are few
flags that initial states are dependant on the source of reset. User can recognize the cause of reset by
reading the flags. There are three ways of putting the device into reset state. They are External reset,
Power on reset and Watchdog reset.
External Reset
The device continuously samples the RESET pin at state C4 of every machine cycle. Therefore, the
RESET pin must be held for at least 2 machine cycles to ensure detection of a valid RESET high. The
reset circuitry then synchronously applies the internal reset signal. Thus, the reset is a synchronous
operation and requires the clock to be running to cause an external reset.
Once the device is in reset condition, it will remain so as long as RESET is 1. Even after RESET is
deactivated, the device will continue to be in reset state for up to two machine cycles, and then begin
program execution from 0000h. There is no flag associated with the external reset condition. However,
since some flags indicate the cause of other two reset, the external reset can be considered as the
default reset if those two flags are cleared.
Watchdog Timer Reset
The Watchdog timer is a free running timer with programmable time-out intervals. The user can reset
the watchdog timer at any time to avoid producing the flag WDIF. If the Watchdog reset is enabled and
the flag WDIF is set high, the watchdog timer reset is performed after the additional 512 clocks come.
This places the device into the reset condition. The reset condition is maintained by hardware for two
machine cycles. Once the reset is removed, the device will begin execution from 0000h.
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