W925EP01 Datasheet, PDF (54/108 Pages) Winbond – 8-BIT CID MICROCONTROLLER

W925EP01/ W925EP01FG
CLOCK CONTROL
WD1, WD0: CKCON.7, CKCON.6 - Watchdog Timer Mode select bits. These two bits select the time-
out interval for the watchdog timer. The reset time is longer 512 clocks time than the
interrupt time-out value.
The default Watchdog time-out is 2¹² clocks, which is the shortest time-out period.
6.9 Serial Port
SERIAL PORT0
Serial port0 in the W925EP01 is a full duplex port. The W925EP01 provides the user with additional
features such as the Frame Error Detection and the Automatic Address Recognition. The serial port0
are capable of synchronous as well as asynchronous communication. In Synchronous mode the
W925EP01 generates the clock and operates in a half duplex mode. In the asynchronous mode, full
duplex operation is available. This means that it can simultaneously transmit and receive data. The
transmit register and the receive buffer are both addressed as SBUF Special Function Register.
However any write to SBUF will be to the transmit register, while a read from SBUF will be from the
receiver buffer register. The serial port0 can operate in four different modes as described below.
MODE 0
This mode provides synchronous communication with external devices. In this mode, serial data is
transmitted and received on the RXD line. TXD is used to transmit the shift clock that is provided by
the W925EP01 whether the device is transmitting or receiving. This mode is therefore a half duplex
mode of serial communication. In this mode, 8 bits are transmitted or received per frame. The LSB is
transmitted or received first. The baud rate is fixed at 1/12 or 1/4 of the oscillator frequency. This baud
rate is determined by the SM2 bit (SCON.5). When bit SM2 is set to zero, the transceiver rate of serial
rate is 1/12 of the clock. When bit SM2 is set to one, the transceiver rate of serial rate is 1/4 of the
clock.
The functional block diagram is shown below. Data enters and leaves the Serial port on the RxD line.
The TxD line is used to output the shift clock. The shift clock is used to shift data into and out of the
W925EP01 and the device at the other end of the line. Any instruction that causes a write to SBUF will
start the transmission. The shift clock will be activated and data will be shifted out on the RxD pin until
all 8 bits are transmitted. If SM2 = 1, then the data on RxD will appear 1 clock period before the falling
edge of shift clock on TxD. The clock on TxD then remains low for 2 clock periods, and then goes high
again. If SM2 = 0, the data on RxD will appear 3 clock periods before the falling edge of shift clock on
TxD. The clock on TxD then remains low for 6 clock periods, and then goes high again. This ensures
that at the receiving end the data on RxD line can either be clocked on the rising edge of the shift
clock on TxD or latched when the TxD clock is low.
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