W925EP01 Datasheet, PDF (45/108 Pages) Winbond – 8-BIT CID MICROCONTROLLER

W925EP01/ W925EP01FG
Table 6 Instruction Timing for W925EP01, continued
Instruction
ORL A, R5
ORL A, R6
ORL A, R7
ORL A, @R0
ORL A, @R1
ORL A, direct
ORL A, #data
ORL direct, A
ORL direct, #data
ORL C, bit
ORL C, /bit
PUSH direct
POP direct
RET
RETI
HEX
Op-Code
4D
4E
4F
46
47
45
44
42
43
72
A0
C0
D0
22
32
Bytes
Machine
Cycles
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
3
3
2
2
2
2
2
2
2
2
1
2
1
2
Instruction
XCH A, direct
XRL A, R0
XRL A, R1
XRL A, R2
XRL A, R3
XRL A, R4
XRL A, R5
XRL A, R6
XRL A, R7
XRL A, @R0
XRL A, @R1
XRL A, direct
XRL A, #data
XRL direct, A
XRL direct, #data
HEX
Op-Code
C5
68
69
6A
6B
6C
6D
6E
6F
66
67
65
64
62
63
Bytes
Machine
Cycles
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
3
3
6.5 Power Management
The W925EP01 has 3 operation mode, normal mode, idle mode and power down mode to manage
the power consumption.
Normal Mode
Normal mode is used in the normal operation status. All functions can be worked in the normal mode.
Idle Mode
The user can put the device into idle mode by writing 1 to the bit PCON.0. The instruction that sets the
idle bit is the last instruction that will be executed before the device goes into Idle Mode. In the Idle
mode, the clock to the CPU is halted, but not to the Interrupt, Timer, Watchdog timer, Divider,
Comparator and CID blocks. This forces the CPU state to be frozen; the Program counter, the Stack
Pointer, the Program Status Word, the Accumulator and the other registers hold their contents. The
port pins hold the logical states they had at the time Idle was activated. The Idle mode can be
terminated in two ways. Since the interrupt controller is still active, the activation of any enabled
interrupt can wake up the processor. This will automatically terminate the idle mode and clear the idle
bit. And if bit IDLT (PCON.4) is cleared the Interrupt Service Routine (ISR) will be executed, else the
idle mode is released directly without any execution of ISR. After the ISR, execution of the program
will continue from the instruction, which put the device into idle mode.
The Idle mode can also be exited by activating the reset. The device can be put into reset by either
applying a low on the external RESET pin or a power on/fail reset condition or a Watchdog timer reset.
The external reset pin has to be held low for at least two machine cycles i.e. 8 clock periods to be
recognized as a valid reset. In the reset, condition the program counter is reset to 0000h and all the
SFRs are set to the reset condition. Since the clock is still running in the period of external reset
therefore the instruction is executed immediately. In the Idle mode, the Watchdog timer continues to
run, and if enabled, a time-out will cause a watchdog timer interrupt, which will wake up the device.
The software must reset the Watchdog timer in order to preempt the reset, which will occur after 512
clock periods of the time-out.
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Publication Release Date: Apr. 10, 2006
Revision A2