W925EP01 Datasheet, PDF (42/108 Pages) Winbond – 8-BIT CID MICROCONTROLLER

W925EP01/ W925EP01FG
6.4 Instruction
The W925EP01 executes all the instructions of the standard 8032 family. However, timing of these
instructions is different. In the W925EP01, each machine cycle consists of 4 clock periods, while in the
standard 8032 it consists of 12 clock periods. Also, in the W925EP01 there is only one fetch per
machine cycle i.e. 4 clocks per fetch, while in the standard 8032 there can be two fetches per machine
cycle, which works out to 6 clocks per fetch.
Table 2 Instructions that affect Flag settings
INSTRUCTION
CARRY
AUXILIARY
OVERFLOW
CARRY
INSTRUCTION
CARRY
INC, DEC
-
-
-
SETB C
1
ADD
X
X
X
CLR C
0
ADDC
X
X
X
CPL C
X
SUBB
X
X
X
ANL C, bit
X
MUL
0
X
ANL C, bit
X
DIV
0
X
ORL C, bit
X
DA A
X
ORL C, bit
X
RRC A
X
MOV C, bit
X
RLC A
X
CJNE
X
A "X" indicates that the modification is as per the result of instruction.
A "-" indicates that the flag is not effected by the instruction.
OVERFLOW
AUXILIARY
CARRY
Instruction
NOP
ADD A, R0
ADD A, R1
ADD A, R2
ADD A, R3
ADD A, R4
ADD A, R5
ADD A, R6
ADD A, R7
ADD A, @R0
ADD A, @R1
ADD A, direct
ADD A, #data
ADDC A, R0
ADDC A, R1
ADDC A, R2
ADDC A, R3
ADDC A, R4
ADDC A, R5
ADDC A, R6
ADDC A, R7
Table 3 Instruction Timing for W925EP01
HEX
Op-Code
Bytes
Machine
Cycles
Instruction
00
1
1
ANL A, R0
28
1
1
ANL A, R1
29
1
1
ANL A, R2
2A
1
1
ANL A, R3
2B
1
1
ANL A, R4
2C
1
1
ANL A, R5
2D
1
1
ANL A, R6
2E
1
1
ANL A, R7
2F
1
1
ANL A, @R0
26
1
1
ANL A, @R1
27
1
1
ANL A, direct
25
2
2
ANL A, #data
24
2
2
ANL direct, A
38
1
1
ANL direct, #data
39
1
1
ANL C, bit
3A
1
1
ANL C, /bit
3B
1
1
CJNE A, direct, rel
3C
1
1
CJNE A, #data, rel
3D
1
1
CJNE @R0, #data, rel
3E
1
1
CJNE @R1, #data, rel
3F
1
1
CJNE R0, #data, rel
HEX
Op-Code
58
59
5A
5B
5C
5D
5E
5F
56
57
55
54
52
53
82
B0
B5
B4
B6
B7
B8
Bytes
Machine
Cycles
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
3
3
2
2
2
2
3
4
3
4
3
4
3
4
3
4
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