W925EP01 Datasheet, PDF (49/108 Pages) Winbond – 8-BIT CID MICROCONTROLLER

W925EP01/ W925EP01FG
Table 7 Interrupt table.
INTERRUPT
External
interrupt 0
Timer0
overflow
External
interrupt 1
Timer1
overflow
Serial port0
FLAG
NAME
FLAG
LOCATION
EN BIT
IE0 TCON.1 EX0
TF0 TCON.5 ET0
IE1 TCON.3 EX1
TF1 TCON.7 ET1
RI
TI
SCON.0
SCON.1
ES0
EN BIT
LOCATION
IE.0
IE.1
IE.2
IE.3
IE.4
Serial port1 SF1 SCON1.7 ES1
IE.6
External
interrupt 2
External
interrupt 3
CID
Divider
overflow
Compare
difference
Watchdog
timer
IE2
EXIF.0
EX2
IE3
CIDF
DIVF
EXIF.1
EXIF.2
EXIF.3
EX3
ECID
EDIV
COMPF EXIF.4 ECOMP
WDIF WDCON.3 EWDI
EIE.0
EIE.1
EIE.2
EIE.3
EIE.4
EIE.5
PRIORITY
1
(higest)
2
3
4
5
6
7
8
9
10
11
12
(lowest)
FLAG CLEARED INTERRUPT
BY
VECTOR
hardware +
software
03h
hardware +
software
0Bh
hardware +
software
13h
hardware +
software
1Bh
hardware +
software
23h
hardware +
software
3Bh
hardware +
software
43h
hardware +
software
4Bh
software
53h
hardware +
software
5Bh
hardware +
software
63h
software
6Bh
Ps: The flags marked as the italic font are not bit-addressable.
The interrupt flags are sampled every machine cycle. In the same machine cycle, the sampled
interrupts are polled and their priority is resolved. If certain conditions are met then the hardware will
execute an internally generated LCALL instruction which will vector the process to the appropriate
interrupt vector address. The conditions for generating the LCALL are
1. An interrupt of equal or higher priority is not currently being serviced.
2. The current polling cycle is the last machine cycle of the instruction currently being executed.
3. The current instruction does not involve a write to IP, IE, EIP or EIE registers and is not a RETI.
If any of these conditions is not met, then the LCALL will not be generated. The polling cycle is
repeated every machine cycle, with the interrupts being sampled in the same machine cycle. If an
interrupt flag is active in one cycle but not responded to, and is not active when the above conditions
are met, the denied interrupt will not be serviced. This means that active interrupts are not
remembered. Note that every polling cycle is new.
Execution continues from the vectored address until an RETI instruction is executed. On execution of
the RETI instruction, the processor pops out the top content of Stack to the PC. The processor is not
notified anything if the content of stack was changed. Note that a RET instruction would perform
exactly the same process as a RETI instruction, but it would not inform the Interrupt Controller that the
interrupt service routine is completed, and would leave the controller still thinking that the service
routine is underway.
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Publication Release Date: Apr. 10, 2006
Revision A2