W925EP01 Datasheet, PDF (55/108 Pages) Winbond – 8-BIT CID MICROCONTROLLER

W925EP01/ W925EP01FG
Fosc/2
12
4
SM2
01
RI
REN
Write to
SBUF
Internal
Data Bus
TX START TX SHIFT
TX CLOCK
TI
SERIAL
CONTROLLE ^RI
RX
CLOCK
RX
START
SHIFT
CLOCK
LOAD SBUF
RX SHIFT
PARIN SOUT
LOAD
CLOCK
RXD
P3.0 Alternate
Output Function
Transmit Shift Register
Serial Port Interrupt
TXD
P3.1 Alternate
Output function
Read SBUF
RXD
P3.0 Alternate
Iutput function
CLOCK
PAROUT
SIN
SBUF
Internal
Data Bus
Receive Shift Register
Figure 6-8 Serial Port 0 Mode 0
MODE 1
In Mode 1, the full duplex asynchronous mode is used. Serial communication frames are made up of
10 bits that are transmitted on TXD and received on RXD. The 10 bits consist of a start bit (0), 8 data
bits (LSB first), and a stop bit (1). On receive, the stop bit goes into RB8(SCON.3). The baud rate in
this mode is variable. The serial baud rate can be programmed as 1/16 or 1/32 of the Timer 0 or 1
overflow, or 1/16 of the baud rate generator counter (BG-counter) overflow. In mode 1, the SM2
(SCON.5) must be cleared.
Transmission begins with a write to SBUF. The serial data is brought out on to TxD pin at C1 following
the first rollover of divide by 16 bit counter. The next bit is placed on TxD pin at C1 following the next
rollover of the divide by 16 bit counter. Thus, the transmission is synchronized to the divide by 16 bit
counter and not directly to the write to SBUF signal. After all 8 bits data has been transmitted, the stop
bit is transmitted. The TI flag is set in the C1 state after the stop bit has been put out on TxD pin. This
will be at the 10th rollover of the divide by 16 bit counter after a write to SBUF.
Reception is enabled only if REN is high. The serial port actually starts the receiving of serial data,
with the detection of a falling edge on the RxD pin. The 1-to-0 detector continuously monitors the RxD
line, sampling it at the rate of 16 times the selected baud rate. When a falling edge is detected, the
divide by 16 bit counter is immediately reset. This helps to align the bit boundaries with the rollovers of
the divide by 16 bit counter.
The 16 states of the counter effectively divide the bit time into 16 slices. The bit detection is done on a
best of three bases. The bit detector samples the RxD pin, at the 8th, 9th and 10th counter states. By
using a majority 2 of 3 voting system, the bit value is selected. This is done to improve the noise
rejection feature of the serial port. If the first bit detected after the falling edge of RxD pin is not 0, then
this indicates an invalid start bit, and the reception is immediately aborted. The serial port again looks
for a falling edge in the RxD line. If a valid start bit is detected, then the rest of the bits are also
detected and shifted into the SBUF.
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Publication Release Date: Apr. 10, 2006
Revision A2