W925EP01 Datasheet, PDF (28/108 Pages) Winbond – 8-BIT CID MICROCONTROLLER

W925EP01/ W925EP01FG
P5 I/O PORT CONTROL
(initial=FFH, input mode)
Bit:
7
6
5
4
3
2
1
0
P5.7IO P5.6IO P5.5IO P5.4IO P5.3IO P5.2IO P5.1IO P5.0IO
Mnemonic: P5IO
P5IO: P5 pins I/O control.
1: input mode
0: output mode
PORT 3
Address: AFh
(initial=FFH)
Bit:
7
6
5
4
3
2
1
0
P3.7 P3.6 P3.5 P3.4 P3.3 P3.2 P3.1 P3.0
Mnemonic: P3
Address: B0h
P3.7-0: P3 can be selected as input or output mode by the P3IO register, at initial reset, P3IO is set to
1, P3 is used as input mode. When P3IO is set to 0, the P3 is used as CMOS output mode.
Special function of P3 is described below.
P3.7
RD
Read low pulse signal when reading external RAM
P3.6
WR
Write low pulse signal when writing external RAM
P3.5
T1
Timer/counter 1 external count input
P3.4
T0
Timer/counter 0 external count input
P3.3
INT1
External interrupt 1
P3.2
INT0
External interrupt 0
P3.1
TxD
Serial port0 output
P3.0
RxD
Serial port0 input
CID REGISTER
(initial=00H, read only)
Bit:
7
6
5
4
3
2
1
0
-
FCLK FDATA FCD DTMFD FDR ALGO RNG
Mnemonic: CIDR
Address: B1h
This SFR indicates the CID signal immediately. Register data is set or cleared by hardware only.
FCLK: FSK serial clock with the baud rate of 1200Hz.
FDATA: FSK serial bit data.
FCD: Set when FSK carrier is detected. Cleared when FSK carrier is disappeared.
DTMFD: Set when DTMF decoded data is ready. Cleared when DTMF signal ends.
FDR: Set when FSK 8 bits data is ready. Cleared before next FSK start bit comes
ALGO: Dual tone Alert signal Guard time detect signal. Set when a guard time qualified dual tone
alert signal has been detected. Cleared when the guard time qualified dual tone alert signal is
absent.
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