W925EP01 Datasheet, PDF (47/108 Pages) Winbond – 8-BIT CID MICROCONTROLLER

W925EP01/ W925EP01FG
6.7 Interrupt
The W925EP01 has a two priority levels interrupt structure with 12 interrupt sources. Each of the
interrupt sources has an individual priority bit, flag, interrupt vector and enable bit. In addition, the
interrupts can be globally enabled or disabled.
Interrupt Sources
The External Interrupts INT0 and INT1 can be either edge triggered or level triggered, depending
on bits IT0 and IT1. The bits IE0 and IE1 in the TCON register are the flags, which are checked to
generate the interrupt. In the edge triggered mode of the INT0 and the INT1 inputs are sampled in
every machine cycle. If the sample is high in one cycle and low in the next, then a high to low
transition is detected and the interrupts request flag IEx in TCON is set. The flag bit requests the
interrupt. Since the external interrupts are sampled every machine cycle, they have to be held high or
low for at least one complete machine cycle. The IEx flag is automatically cleared when the service
routine is called. If the level triggered mode is selected, then the requesting source has to hold the pin
low until the interrupt is serviced. The IEx flag will not be cleared by the hardware on entering the
service routine. If the interrupt continues to be held low even after the service routine is completed,
then the processor may acknowledge another interrupt request from the same source. Note that the
external interrupts INT2 to INT3 are edge triggered only.
The TF0, TF1 flags generate the Timer 0, 1 Interrupts. These flags are set by the overflow in the
Timer 0, Timer 1. The TF0 and TF1 flags are automatically cleared by the hardware when the timer
interrupt is serviced.
The Watchdog timer can be used as a system monitor or a simple timer. In either case, when the
time-out count is reached, the Watchdog timer interrupt flag WDIF (WDCON.3) is set. If the enable bit
EIE.5 enables the interrupt, then an interrupt will occur.
The Serial block can generate interrupts on reception or transmission. There are two interrupt sources
from the Serial block, which are obtained by the RI and TI bits in the SCON SFR and SF1 in the
SCON1 SFR. RI and TI are not automatically cleared by the hardware, and the user will have to clear
these bits using software, SF1 is cleared automatically when the serial port1 interrupt is serviced.
The divider interrupt is generated by DIVF that is set when divider overflows. DIVF is set by hardware
and cleared when divider interrupt is serviced. The divider interrupt is enable/disable if the bit EDIV is
high/low.
The comparator interrupt is produced by COMPF, which is set when the RESC bit is changed from
low to high. RESC, which is the real-time result of comparator, set when the voltage of reference input
is higher than the voltage of analog input.
The CID interrupt is generated by CIDF. The CIDF is a logic OR output of all CID flags which are set
by hardware and cleared by software. The structure of the CID flags is shown in Figure 6-4.
Each of the individual interrupts can be enabled or disabled by setting or clearing the corresponding
bits in the IE and EIE SFR. A bit EA, which is located in IE.7, is a global control bit to enable/disable
the all interrupt. When bit EA is zero all interrupts are disabling and when bit EA is high, each interrupt
is enabled individually by the corresponding bit.
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Publication Release Date: Apr. 10, 2006
Revision A2