W925EP01 Datasheet, PDF (66/108 Pages) Winbond – 8-BIT CID MICROCONTROLLER

W925EP01/ W925EP01FG
6.15 Divider
A built-in 13/14-bit binary up counter designed to generate periodic interrupt. The clock source is from
sub-oscillator. When the frequency of sub-crystal is 32768Hz, it provides the divider interrupt in the
period of 0.25/0.5 second. Bit DIVS controls the degree of divider. When DIVA is set to high, it will
enable the divided counter; when DIVA is low to reset divider and stop counting. As the divider
overflows, the divider interrupt flag DIVF is set. DIVF is clear by software or serving divider interrupt
routine.
DIVS
(CKCON1.1)
Fs
1
DIVA
(DIVC.0)
overflow
11
34
Executing DIV Int
Clear by software
D
Q
ck
CR
DIVF
(EXIF.3
)
Figure 6-11 13/14-bit Divider
6.16 Timed Access Protection
The W925EP01 has a new feature, CHPCON for ISP function, which are crucial to proper operation of
the system. If left unprotected, errant code may write to the CHPCON control bits resulting in incorrect
operation and loss of control. In order to prevent this, the W925EP01 has a protection scheme that
controls the write access to critical bits. This protection scheme is done using a timed access.
In this method, the bits that are to be protected have a timed write enable window. A write is
successful only if this window is active, otherwise the write will be discarded. This write enable window
is open for 3 machine cycles if certain conditions are met. After 3 machine cycles, this window
automatically closes. The window is opened by writing AAh and immediately 55h to the Timed
Access(TA) SFR. This SFR is located at address C7h. The suggested code for opening the timed
access window is
TA
REG
EEh
;define new register TA, located at 0EEh
MOV
TA, #AAh
MOV
TA, #55h
When the software writes AAh to the TA SFR, a counter is started. This counter waits for 3 machine
cycles looking for a write of 55h to TA. If the second write (55h) occurs within 3 machine cycles of the
first write (AAh), then the timed access window is opened. It remains open for 3 machine cycles,
during which the user may write to the protected bits. Once the window closes the procedure must be
repeated to access the other protected bits.
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