W925EP01 Datasheet, PDF (11/108 Pages) Winbond – 8-BIT CID MICROCONTROLLER

W925EP01/ W925EP01FG
Interrupts:
The W925EP01 provides 12 interrupt resources with two priority levels, including 4 external interrupt
sources, 2 timer interrupts, 1 CID interrupt, 1 divider interrupt, 2 serial port interrupt, 1 comparator
interrupt and 1 watchdog timer interrupt.
Power Management:
The W925EP01 has IDLE and POWER DOWN modes of operation. In the IDLE mode, the clock to
the CPU core is stopped however the functions of the timers, divider, CID and interrupts are active
continuously. In the POWER DOWN mode, both of the system clocks stop oscillating and the chip
operation is completely stopped. POWER DOWN mode is the state of the lowest power consumption.
6.1 Memory Organization
The W925EP01 separates the memory into two separate sections, the Program Memory and the Data
Memory. The Program Memory is used to store the instruction op-codes and look-up table data, while
the Data Memory is used to store data or for memory mapped devices.
Program Memory:
The W925EP01 is an 8-bit micro controller which has an in-system programmable EPROM for
firmware updating. The instruction set of the W925EP01 is fully compatible with the standard 8052.
The W925EP01 contains a 64K bytes of main EPROM and a 4K bytes of auxiliary Flash EPROM
which allows the contents of the 64KB main EPROM to be updated by the loader program located at
the 4KB auxiliary Flash EPROM. To facilitate programming and verification, the EPROM inside the
W925EP01 allows the program memory to be programmed and read electronically. Once the code is
confirmed, the user can protect the code for security.
The Program Memory on the W925EP01 can be up to 128K bytes. That is 64K bytes of on chip in-
system programmable Flash EPROM (APROM) for Application Program and 64K bytes of external
program ROM for code or data memory expansion.
The 4K bytes of auxiliary Flash EPROM (LDROM) are for Loader Program.
The whole 128K can be used to store look-up table data. Because the op-code is 64K addressable, a
PG bit in PAGE register decides which ROM page between page0, page1 is enabled, and the ALU
fetches the op-code from the selected ROM page. If PG=0, ALU fetches the op-code from page0. If
PG=1, ALU fetches the op-code from page1. When MOVC instruction is executed, ALU fetches the
look-up table data according the indication of LT bits. The value of LT indicates which ROM page is
active for look-up table instruction.
1FFFF
10000
0FFFF
00000
64K External
Program ROM
Page1
64K APROM
Page0
PG=1
PG=0
LT=1
LT=0
FFF
4K
LDROM
000
Figure 6-1 Program Memory Map
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Publication Release Date: Apr. 10, 2006
Revision A2