W83787IF Datasheet, PDF (78/123 Pages) Winbond – WINBOND I/O WITH SERIAL-INFRARED SUPPORT

W83787IF
7.2.15 Configuration Register E, F (CR0E, CR0F) EFER = 89H, EFIR = 0EH, 0FH
Bit 7~ Bit 0: Reserved for testing.
7.2.16 Configuration Register 10H (CR10) EFER = 89H, EFIR = 10H (R/W)
When 89H is loaded into EFER and 10H is loaded into EFIR, the CR10 register can be accessed
through EFDR. The bit definitions are as follows:
7 65 4 3 210
GIO0AD0
GIO0AD1
GIO0AD2
GIO0AD3
GIO0AD4
GIO0AD5
GIO0AD6
GIO0AD7
Notes:
GIO0ADR7~0 (Bit 7 ~ Bit0):
These 8 bits select GIO0 (Pin 92) address bit 7 ~ bit 0, another GIO0 address bit 10 ~ bit 8 are
defined in CR11 bit 3 ~ bit 0.
7.2.17 Configuration Register 11H (CR11) EFER = 89H, EFIR = 11H (R/W)
When 89H is loaded into EFER and 11H is loaded into EFIR, the CR11 register can be accessed
through EFDR. The bit definitions are as follows:
7 65 4 3 210
GIO0AD8
GIO0AD9
GIO0AD10
Reserved
Reserved
Reserved
GIO0 ADR MODE0
GIO0 ADR MODE1
Notes:
GIO0 ADR MODE1 ~ 0 (Bit7 ~ Bit6):
These two bits select address mode. (Defined as following table)
GIO0 ADR MODE1 ~ 0
00
01
10
11
Decode Mode
1 byte decode (Compare GIO0ADR10~0 with SA10~0)
2 bytes decode (Compare GIO0ADR10~1 with SA10~1)
4 bytes decode (Compare GIO0ADR10~2 with SA10~2)
8 bytes decode (Compare GIO0ADR10~3 with SA10~3)
Bit 5 ~ Bit 3: Reserved.
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Publication ReleaseDate:Sep 1995
Revision A1