W83787IF Datasheet, PDF (35/123 Pages) Winbond – WINBOND I/O WITH SERIAL-INFRARED SUPPORT

W83787IF
3.0 IDE
The IDE interface is essentially the AT bus ported to the hard disk drive. The hard disk controller
resides on the IDE hard disk drive. So the IDE interface provides only chip select signals and AT bus
signals between the IDE hard disk drive and ISA slot. Table 3-1 shows the IDE registers and their ISA
addresses.
Table 3-1
I/O ADDRESS
PRIMARY
SECONDARY
1F0
170
1F1
171
1F2
172
1F3
173
1F4
174
1F5
175
1F6
176
1F7
177
3F6
376
3F7
377
READ
REGISTERS
WRITE
Data Register
Data Register
Error Register
Write-Precomp
Sector Count
Sector Count
Sector Number
Sector Number
Cylinder LOW
Cylinder LOW
Cylinder HIGH
Cylinder HIGH
SDH Register
SDH Register
Status Register
Command Register
Alternate Status
Fixed Disk Control
Digital Input
Undefined
3.1 IDE Decode Description
When the processor selects Ports 1F0-1F7 (or 170-177), the chip system enables CS0 = LOW;
otherwise, CS0 = HIGH. When the processor selects Ports 3F6-3F7 (or 376-377), the chip system
enables CS1 = LOW; otherwise, CS1 = HIGH.
4.0 UART PORT
4.1 Universal Asynchronous Receiver/Transmitter (UART A, UART B)
The UARTs are used to convert parallel data into serial format on the transmit side and convert serial
data to parallel format on the receiver side. The serial format, in order of transmission and reception,
is a start bit, followed by five to eight data bits, a parity bit (if programmed) and one, one and half
(five-bit format only) or two stop bits. The UARTs are capable of handling divisors of 1 to 65536 and
producing a 16x clock for driving the internal transmitter logic. Provisions are also included to use this
16x clock to drive the receiver logic. The UARTs also support the MIDI data rate. Furthermore, the
UARTs also include complete modem control capability and a processor interrupt system that may be
software trailed to the computing time required to handle the communication link. The UARTs have a
FIFO mode to reduce the number of interrupts presented to the CPU. In each UART, there are 16-
byte FIFOs for both receive and transmit mode.
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Publication Release Date:Sep 1995
Revision A1