W83787IF Datasheet, PDF (53/123 Pages) Winbond – WINBOND I/O WITH SERIAL-INFRARED SUPPORT

W83787IF
5.3.4 Device Control Register (DCR)
The bit definitions are as follows:
7 65 432 1 0
11
strobe
autofd
nInit
SelectIn
ackIntEn
Direction
Notes:
Bit 6, 7: These two bits are logic one during a read and cannot be written.
Bit 5: This bit has no effect and the direction is always out if mode = 000 or mode = 010. Direction is
valid in all other modes.
0 the parallel port is in output mode.
1 the parallel port is in input mode.
Bit 4: Interrupt request enable. When this bit is set to a high level, it may be used to enable interrupt
requests from the parallel port to the CPU due to a low to high transition on the ACK input.
Bit 3: This bit is inverted and output to the SLIN output.
0 The printer is not selected.
1 The printer is selected.
Bit 2: This bit is output to the INIT output.
Bit 1: This bit is inverted and output to the AFD output.
Bit 0: This bit is inverted and output to the STB output.
5.3.5 cFifo (Parallel Port Data FIFO) Mode = 010
This mode is defined only for the forward direction. The standard parallel port protocol is used by a
hardware handshake to the peripheral to transmit bytes written or DMAed from the system to this
FIFO. Transfers to the FIFO are byte aligned.
5.3.6 ecpDFifo (ECP Data FIFO) Mode = 011
When the direction bit is 0, bytes written or DMAed from the system to this FIFO are transmitted by a
hardware handshake to the peripheral using the ECP parallel port protocol. Transfers to the FIFO are
byte aligned.
When the direction bit is 1, data bytes from the peripheral are read under automatic hardware
handshake from ECP into this FIFO. Reads or DMAs from the FIFO will return bytes of ECP data to
the system.
5.3.7 tFifo (Test FIFO Mode) Mode = 110
Data bytes may be read, written, or DMAed to or from the system to this FIFO in any direction.
Data in the tFIFO will not be transmitted to the parallel port lines. However, data in the tFIFO may be
displayed on the parallel port data lines.
5.3.8 cnfgA (Configuration Register A) Mode = 111
This register is a read-only register. When it is read, 10H is returned. This indicates to the system that
this is an 8-bit implementation.
- 53 -
Publication ReleaseDate:Sep 1995
Revision A1