W83787IF Datasheet, PDF (75/123 Pages) Winbond – WINBOND I/O WITH SERIAL-INFRARED SUPPORT

W83787IF
PEXTECP (Bit 1):
This bit controls whether the PEXTEN pin is active in ECP mode.
0
PEXTEN is not active in ECP mode
1
PEXTEN is active in ECP mode
PEXTECPP (Bit 0):
This bit controls whether the PEXTEN pin is active in ECP/EPP mode.
0
PEXTEN is not active in ECP/EPP mode
1
PEXTEN is active in ECP/EPP mode
7.2.12 Configuration Register B (CRB) EFER = 89H, EFIR = 0BH
This register is reserved.
7.2.13 Configuration Register C (CR0C) EFER = 89H, EFIR = 0CH (R/W)
When 89H is loaded into EFER and 0CH is loaded into EFIR, the CRC register can be accessed
through EFDR. The bit definitions are as follows:
7 65 4 3 210
TX2INV
RX2INV
IDEGIOSEL
URIRSEL
Reserved
HEFERE
TURB
TURA
Notes:
TURA (Bit 7):
This bit is represent the clcok source of UART A.
0 The clock source is 1.8462MHZ (24 MHZ divide 13). Hence, the maximum baud rate
of UART A is 115.2K bps. (Default)
1 The clock source is 24MHZ, that is, the maximum baud can be obtained 24/16 MHZ. This
can be used in loopback testing or higher data transfer.
TURB (Bit 6):
This bit is the clock source of UART B described as Bit7.
HEFERE (Bit5):
This bit is EFER enable value.
0 The Extended Function Enable Register (EFER) enable value is set to 88H.
1 The Extended Function Enable Register (EFER) enable value is set to 89H.
During power-on reset, the default vaule is set by the Pin 41 (GMRD#) pulled high or low. This pin is
internal pull-high.
Bit 4: Reserved
- 75 -
Publication ReleaseDate:Sep 1995
Revision A1