W83787IF Datasheet, PDF (68/123 Pages) Winbond – WINBOND I/O WITH SERIAL-INFRARED SUPPORT

W83787IF
PRTTRI (Bit 3):
This bit enables or disables the tri-state outputs of parallel port in power-down mode.
0
The output pins of the parallel port will not be tri-stated when parallel port is in power-
down mode.
1
The output pins of the parallel port will be tri-stated when parallel port is in power-
down mode.
GMTRI (Bit 2):
This bit enables or disables the tri-state outputs of the game port in power-down mode.
0
The output pins of the game port will not be tri-stated when game port is in power-
down mode.
1
The output pins of the game port will be tri-stated when game port is in power-down
mode.
URATRI (Bit 1):
This bit enables or disables the tri-state outputs of UARTA in power-down mode.
0
The output pins of UARTA will not be tri-stated when UARTA is in power-down mode.
1
The output pins of UARTA will be tri-stated when UARTA is in power-down mode.
URBTRI (Bit 0):
This bit enables or disables the tri-state outputs of UARTB in power-down mode.
0
The output pins of UARTB will not be tri-stated when UARTB is in power-down mode.
1
The output pins of UARTB will be tri-stated when UARTB is in power-down mode.
7.2.6 Configuration Register 5 (CR5) EFER = 89H, EFIR = 05H
When 89H is loaded into EFER and 05H is loaded into EFIR, the CR5 register can be accessed
through EFDR. The bit definitions are as follows:
7 6 54 3 2 1 0
ECP FTHR0
ECP FTHR1
ECP FTHR2
ECP FTHR3
Reserved
Reserved
Reserved
Reserved
Notes:
Bit 7-4: Reserved
Bit 3-0: These four bits define the FIFO threshold for the ECP mode parallel port. The default value is
0000 after power-up.
7.2.7 Configuration Register 6 (CR6) EFER = 89H, EFIR = 06H
When 89H is loaded into EFER and 06H is loaded into EFIR, the CR6 register can be accessed
through EFDR. The bit definitions are as follows:
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Publication ReleaseDate:Sep 1995
Revision A1