W83787IF Datasheet, PDF (42/123 Pages) Winbond – WINBOND I/O WITH SERIAL-INFRARED SUPPORT

W83787IF
TABLE 4-5 INTERRUPT CONTROL FUNCTION
ISR
INTERRUPT SET AND FUNCTION
Bit Bit Bit Bit Interrupt Interrupt Type
3 2 1 0 priority
Interrupt Source
Clear Interrupt
0 001
-
0 1 1 0 First
-
UART Receive
Status
0 1 0 0 Second RBR Data Ready
1 1 0 0 Second FIFO Data Timeout
0 0 1 0 Third
TBR Empty
0 0 0 0 Fourth Handshake status
** Bit 3 of ISR is enabled when bit 0 of UFR is logical 1.
No Interrupt pending
1. OER = 1 2. PBER =1
3. NSER = 1 4. SBD = 1
1. RBR data ready
2. FIFO interrupt active level
reached
Data present in RX FIFO for 4
characters period of time since last
access of RX FIFO.
TBR empty
1. TCTS = 1 2. TDSR = 1
3. FERI = 1 4. TDCD = 1
-
Read USR
1. Read RBR
2. Read RBR until FIFO
data under active level
Read RBR
1. Write data into TBR
2. Read ISR (if priority is
third)
Read HSR
4.2.7 Interrupt Control Register (ICR) (Read/Write)
This 8-bit register allows the five types of controller interrupts to activate the interrupt output signal
separately. The interrupt system can be totally disabled by resetting bits 0 through 3 of the Interrupt
Control Register (ICR). A selected interrupt can be enabled by setting the appropriate bits of this
register to a logical 1.
7 65 4 3 2 1 0
00 00
RBR data ready interrupt enable (ERDRI)
TBR empty interrupt enable (ETBREI)
UART receive status interrupt enable (EUSRI)
Handshake status interrupt enable (EHSRI)
Notes:
Bit 7-4: These four bits are always logic 0.
Bit 3: EHSRI. Setting this bit to a logical 1 enables the handshake status register interrupt.
Bit 2: EUSRI. Setting this bit to a logical 1 enables the UART status register interrupt.
Bit 1: ETBREI. Setting this bit to a logical 1 enables the TBR empty interrupt.
Bit 0: ERDRI. Setting this bit to a logical 1 enables the RBR data ready interrupt.
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Publication Release Date:Sep 1995
Revision A1