W83787IF Datasheet, PDF (66/123 Pages) Winbond – WINBOND I/O WITH SERIAL-INFRARED SUPPORT

W83787IF
Examples (debug instructions):
Example 7.6: Enable IDE, FDC; enable extension adapter mode (assume I/O port is 300H).
- O 250 89
- O 251 00
- O 252 58 (Set Extension Adapter Mode)
- O 251 02 (XRD and XWR will be active low and C0H will appear at XD1- XD7)
- O 252 C0 (Compare EA3-EA9)
- O 250 00
Example 7.7: Each time host reads/writes 300H-307H, XRD or XWR is active.
In DMA cycles, IOR/W activates DACKX, which will also activate XRD or XWR
separately.
7.2.4 Configuration Register 3 (CR3) EFER = 89, EFIR = 3H
When 89H is loaded into EFER and 03H is loaded into EFIR, the CR3 register can be accessed
through EFDR. The bit definitions are as follows:
7654321 0
SUBMIDI
SUAMIDI
URBS2
URAS2
GMODS
EPPVER
GMENL
PRTBEN
Notes:
SUBMIDI (Bit 0):
This bit selects the clock divide rate of UARTB.
0
disables MIDI support, UARTB clock = 24MHz divided by 13 (default)
1
enables MIDI support, UARTB clock = 24MHz divided by 12
SUAMIDI (Bit 1):
This bit selects the clock divide rate of UARTA.
0
Disables MIDI support, UARTA clock = 24MHz divided by 13 (default)
1
Enables MIDI support, UARTA clock = 24MHz divided by 12
URBS2 (Bit 2):
This bit determines the base address of UARTB.
0
Refer to the description of CR1 bit 1, 3
1
Selects COM1 address, 3F8H
URAS2 (bit 3):
This bit determines the base address of UARTA.
0
Refer to the description of CR1 bit 0, 2
1
Selects COM2 address, 2F8H
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Publication ReleaseDate:Sep 1995
Revision A1