W83787IF Datasheet, PDF (60/123 Pages) Winbond – WINBOND I/O WITH SERIAL-INFRARED SUPPORT

W83787IF
5.7 Joystick Mode*
The joystick mode allows users to plug a joystick into the parallel port DB-25 connector. The pin
definitions are shown in Table 5-1.
Pins NSTB, AFD, NSLIN, and INIT output high as a voltage supply to the joystick.
Pins PD5 and PD4 are the button input of the joystick.
Pins PD1 and PD0 are the X/Y axis paddle input of the joystick.
There are two one-shot timers (556) inside the W83787IF for use with the joystick.
6.0 GAME PORT DECODER
The W83787IF provides GMRD and GMWR pins that decode address 201H and I/O read/write
commands.
If the host issues IOR 201H, the GMRD pin is low active; if it issues IOW 201H, the GMWR pin is low
active.
7.0 EXTENDED FUNCTION REGISTERS
The W83787IF provides many configuration registers for setting up different types of configurations.
After power-on reset, the state of the hardware setting of each pin will be latched by the relevant
configuration register to allow the W83787IF to enter the proper operating configuration. To protect
the chip from invalid reads or writes, the configuration registers cannot be accessed by the user. To
enable the configuration registers to be read and written, first the value 89H/88H must be written to
the Extended Functions Enable Register (I/O port address 250H). Second, a value from 00H to 0BH
must be written to the Extended Functions Index Register (I/O port address 251H) to identify which
configuration register is to be accessed. The user can then access the desired configuration register
through the Extended Functions Data Register (I/O port address 252H). After programming of the
configuration register is finished, a value other than 89H/88H should be written to EFER or bit 6 of
CR9 (LOCKREG) should be set to high to protect the configuration registers against accidental
accesses. The configuration registers can be reset to their default or hardware setting values only by
a cold reset (pin MR = 1). A warm reset will not affect the configuration registers.
7.1 Extended Functions Enable Register (EFER)
After a power-on reset, the W83787IF enters the default operating mode. Before the W83787IF
enters the Extended Function mode, a 89H/88H (dependent on power-on setting value of pin GMRD)
must be programmed to the Extended Function Enable Register (EFER) so that the extended
function register can be accessed. The Extended Function Enable Register is a write-only register. Its
port address is 250H on a PC/AT system.
7.2 Extended Function Index Register(EFIR), Extended Function Data Register(EFDR)
After 89H/88H is programmed into EFER, the Extended Function Index Register (EFIR) must be
loaded with index value 0H, 1H, 2H, ..., or AH to access Configuration Register 0 (CR0),
Configuration Register 1 (CR1), Configuration Register 2 (CR2), ..., or Configuration Register A
(CRA) through the Extended Function Data Register (EFDR). EFIR is a write-only register with port
address 251H on PC/AT systems; EFDR is a read/write register with port address 252H on PC/AT
systems. The function of each configuration register is described below.
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Publication ReleaseDate:Sep 1995
Revision A1