W83787IF Datasheet, PDF (36/123 Pages) Winbond – WINBOND I/O WITH SERIAL-INFRARED SUPPORT

W83787IF
4.2 Register Address
TABLE 4 - 2 UART Register Bit Map
Register Address Base
Bit Number
0
1
2
3
4
5
6
7
8
BDLAB = 0
Receiver
Buffer
Register
(Read Only)
RBR RX Data RX Data RX Data RX Data RX Data RX Data RX Data RX Data
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
8
BDLAB = 0
9
BDLAB = 0
Transmitter
Buffer Register
(Write Only)
Interrupt Control
Register
TBR
ICR
TX Data TX Data
Bit 0
Bit 1
RBR Data TBR
Ready Empty
Interrupt Interrupt
Enable Enable
(ERDRI) (ETBREI)
TX Data
Bit 2
USR
Interrupt
Enable
(EUSRI)
TX Data
Bit 3
HSR
Interrupt
Enable
(EHSRI)
TX Data
Bit 4
0
TX Data
Bit 5
0
TX Data
Bit 6
0
TX Data
Bit 7
0
A
Interrupt Status ISR "0" if Interrupt Interrupt Interrupt
0
Register
Interrupt Status Status Status
(Read Only)
Pending _{Bit (0)}
Bit (1) Bit (2)**
0
FIFOs FIFOs
Enabled Enabled
**
**
A
UART FIFO UFR FIFO RCVR XMIT
DMA Reserved Reversed RX
RX
Control
Enable FIFO
FIFO
Mode
Interrupt Interrupt
Register
Reset Reset Select
Active Active
(Write Only)
Level
Level
(LSB) (MSB)
B
UART Control UCR Data
Data Multiple Parity
Even
Parity
Set Baudrate
Register
Length Length Stop Bits Bit
Parity Bit Fixed Silence Divisor
Select Select Enable Enable Enable Enable Enable Latch
Bit 0
Bit 1 _{(MSBE) (PBE)}
(DLS0) (DLS1)
(EPE) PBFE)
(SSE) ^{Access Bit}
(BDLAB)
C
Handshake HCR Data Request Loopback IRQ Internal
0
0
0
Control
Terminal
to
RI
Enable Loopback
Register
Ready Send
Input
Enable
(DTR) (RTS)
D
UART Status USR RBR Data Overrun Parity Bit No Stop Silent
TBR
TSR RX FIFO
Register
Ready Error
Error
Bit
Byte
Empty Empty
Error
(RDR)
(OER) (PBER) ^{Error Detected} (TBRE) (TSRE) ^Indication
(NSER) (SBD)
(RFEI) **
E
Handshake HSR CTS
DSR RI Falling DCD
Clear Data Set Ring
Data
Status Register
Toggling Toggling Edge Toggling to Send Ready Indicator Carrier
(TCTS) (TDSR) (FERI) (TDCD) (CTS) (DSR)
(RI)
Detect
(DCD)
F
User Defined UDR Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Register
8
Baudrate Divisor BLL Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
BDLAB = 1 ^{Latch Low}
9
Baudrate BHL
BDLAB = 1 ^{Divisor Latch}
High
Bit 8
Bit 9
Bit 10 Bit 11 Bit 12 Bit 13 Bit 14 Bit 15
*: Bit 0 is the least significant bit. The least significant bit is the first bit serially transmitted or received.
**: These bits are always 0 in 16450 Mode.
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Publication Release Date:Sep 1995
Revision A1