W83787IF Datasheet, PDF (63/123 Pages) Winbond – WINBOND I/O WITH SERIAL-INFRARED SUPPORT

W83787IF
• SINA and SINB in idle state
• No register read or write to chip
If all of these conditions are met, a counter begins to count down. While the timer is counting down,
the W83787IF remains in normal operating mode, and if any of the above conditions changes, the
counter will be reset. If the set time (set by bit 7 and bit 6 of CR8) elapses without a change in any of
the above conditions, bits 1 and 0 will be set to (1, 1) and the chip will enter automatic power-down
mode. The oscillator of the W83787IF will remain running, but the internal clock will be disabled to
save power. Once the above conditions are no longer met, the internal clock will be resupplied and
the chip will return to normal operation.
11 Automatic power-down (ADP) state, OSCS2 = 0
The W83787IF enters this state automatically after the counter described above has counted down. If
there is a change in any of the conditions listed above, the W83787IF's clock will be restarted and bits
1 and 0 will be set to (1, 0), i.e., standby for automatic power-down. When the clock is restarted, the
chip is ready for normal operation, with no need to wait for the oscillator to stabilize.
Example 7.1: Enable IDE (1F0H-1F7H, 3F6H, 3F7H), FDC (3F0H-3F7H); W83757 mode: power-on
mode.
Ex. 7.1 (DOS DEBUG.COM inst.)
- O 250 89
- O 251 00
- O 252 50
- O 250 00
Example 7.2: Disable IDE; enable FDC (370H-377H); Extension FDC Mode; immediate power-down
mode.
Ex. 7.2 (DOS DEBUG.COM inst.)
- O 250 89
- O 251 00
- O 252 C5
- O 250 00
Example 7.3: Enable IDE (170H-177H, 376H, 377H), disable FDC; Extension Adapter Mode;
standby for automatic power-down mode.
Ex. 7.3 (DOS DEBUG.COM inst.)
- O 250 89
- O 251 00
- O 252 3A
- O 250 00
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Publication ReleaseDate:Sep 1995
Revision A1