W83787IF Datasheet, PDF (64/123 Pages) Winbond – WINBOND I/O WITH SERIAL-INFRARED SUPPORT

W83787IF
7.2.2 Configuration Register 1 (CR1) EFER = 89H, EFIR = 1H
When 89H is loaded into EFER and 01H is loaded into EFIR, the CR1 register can be accessed
through EFDR. The bit definitions are as follows:
76 5 4 3 2 1 0
URAS0
URBS0
URAS1
URBS1
PTRAS0
PTRAS1
Reserved
ABCHG
Notes:
URAS1 URAS0 (Bit 2, 0):
These two bits and URAS2 (CR3 bit 3) = 0 determine the base address of UARTA. (The default value
depends on SOUTA and DTRB at power-on setting. If there is no setting, UARTA is set to COM1 by
default.) When URAS2 = 1, see the description of CR3 bit 3.
00 Selects COM4 address, 2E8H
01 Selects COM3 address, 3E8H
10 Selects COM1 address, 3F8H
11 Disables UARTA port (when UARTA port is disabled, no clock will be input to this port
in order to save power)
URBS1 URBS0 (Bit 3, 1):
These two bits and URBS2 (CR3 bit 2) = 0 determine the base address of UARTB. (The default value
depends on SOUTB and RTSB at power-on setting. If there is no setting, UARTB is set to COM2 by
default.) When URBS2 = 1, see the description of CR3 bit 2.
00 Selects COM3 address, 3E8H
01 Selects COM4 address, 2E8H
10 Selects COM2 address, 2F8H
11 Disables UARTB port (when UARTB port is disabled, no clock will be input to this port
in order to save power)
PTRAS1, PTRAS0 (Bit 5, 4):
These two bits determine the base address of the parallel port. (The default value depends on RTSA
and DTRA at power-on setting. If there is no setting, the default is LPT1.)
00 Selects LPT3 address, 3BCH
01 Selects LPT2 address, 278H
10 Selects LPT1 address, 378H
11 Disables parallel port all function modes
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Publication ReleaseDate:Sep 1995
Revision A1